390 lines
13 KiB
C
390 lines
13 KiB
C
// Intel High Definition Audio transport declarations shared by the controller and stream implementation.
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#pragma once
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <ntlite/ddi/io_driver.h>
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#include <ntlite/ddi/pci.h>
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#include <ntlite/ddk/ddk.h>
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#define HDA_CONTROLLER_MAGIC 0x4144484Eu
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#define HDA_MAX_CONTROLLERS 8u
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#define HDA_MAX_CODECS 15u
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#define HDA_MAX_NODE_ID 0xFFu
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#define HDA_MAX_UNSOLICITED_RESPONSES 32u
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#define HDA_OUTPUT_SAMPLE_RATE 48000u
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#define HDA_OUTPUT_CHANNELS 2u
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#define HDA_OUTPUT_VALID_BITS 16u
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#define HDA_OUTPUT_BYTES_PER_SAMPLE 2u
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#define HDA_OUTPUT_BYTES_PER_FRAME 4u
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#define HDA_OUTPUT_PERIOD_FRAMES 512u
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#define HDA_OUTPUT_PERIOD_COUNT 4u
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#define HDA_OUTPUT_PERIOD_BYTES (HDA_OUTPUT_PERIOD_FRAMES * HDA_OUTPUT_BYTES_PER_FRAME)
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#define HDA_OUTPUT_BUFFER_BYTES (HDA_OUTPUT_PERIOD_COUNT * HDA_OUTPUT_PERIOD_BYTES)
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#define HDA_OUTPUT_STREAM_FORMAT 0x0011u
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#define HDA_OUTPUT_STREAM_TAG 1u
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#define HDA_MAX_LOGICAL_ENDPOINTS 3u
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#define HDA_REG_GCAP 0x00u
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#define HDA_REG_VMIN 0x02u
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#define HDA_REG_VMAJ 0x03u
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#define HDA_REG_GCTL 0x08u
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#define HDA_REG_STATESTS 0x0Eu
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#define HDA_REG_INTCTL 0x20u
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#define HDA_REG_INTSTS 0x24u
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#define HDA_REG_WALLCLK 0x30u
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#define HDA_REG_CORBLBASE 0x40u
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#define HDA_REG_CORBUBASE 0x44u
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#define HDA_REG_CORBWP 0x48u
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#define HDA_REG_CORBRP 0x4Au
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#define HDA_REG_CORBCTL 0x4Cu
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#define HDA_REG_CORBSTS 0x4Du
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#define HDA_REG_CORBSIZE 0x4Eu
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#define HDA_REG_RIRBLBASE 0x50u
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#define HDA_REG_RIRBUBASE 0x54u
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#define HDA_REG_RIRBWP 0x58u
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#define HDA_REG_RINTCNT 0x5Au
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#define HDA_REG_RIRBCTL 0x5Cu
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#define HDA_REG_RIRBSTS 0x5Du
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#define HDA_REG_RIRBSIZE 0x5Eu
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#define HDA_REG_DPLBASE 0x70u
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#define HDA_REG_DPUBASE 0x74u
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#define HDA_REG_STREAM_BASE 0x80u
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#define HDA_REG_STREAM_STRIDE 0x20u
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#define HDA_GCAP_64OK 0x0001u
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#define HDA_GCAP_BSS_MASK 0x00F8u
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#define HDA_GCAP_BSS_SHIFT 3u
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#define HDA_GCAP_ISS_MASK 0x0F00u
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#define HDA_GCAP_ISS_SHIFT 8u
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#define HDA_GCAP_OSS_MASK 0xF000u
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#define HDA_GCAP_OSS_SHIFT 12u
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#define HDA_GCTL_RESET 0x00000001u
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#define HDA_GCTL_UNSOLICITED_ENABLE 0x00000100u
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#define HDA_INT_CONTROLLER_ENABLE 0x40000000u
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#define HDA_INT_GLOBAL_ENABLE 0x80000000u
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#define HDA_INT_CONTROLLER_STATUS 0x40000000u
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#define HDA_INT_GLOBAL_STATUS 0x80000000u
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#define HDA_CORBRP_POINTER_MASK 0x00FFu
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#define HDA_CORBRP_RESET 0x8000u
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#define HDA_CORBCTL_MEMORY_ERROR_INTERRUPT 0x01u
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#define HDA_CORBCTL_RUN 0x02u
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#define HDA_CORBSTS_MEMORY_ERROR 0x01u
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#define HDA_RIRBWP_RESET 0x8000u
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#define HDA_RIRBCTL_RESPONSE_INTERRUPT 0x01u
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#define HDA_RIRBCTL_RUN 0x02u
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#define HDA_RIRBCTL_OVERRUN_INTERRUPT 0x04u
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#define HDA_RIRBSTS_RESPONSE 0x01u
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#define HDA_RIRBSTS_OVERRUN 0x04u
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#define HDA_RIRB_RESPONSE_CODEC_MASK 0x0000000Fu
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#define HDA_RIRB_RESPONSE_UNSOLICITED 0x00000010u
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#define HDA_RING_SIZE_CAP_2 0x10u
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#define HDA_RING_SIZE_CAP_16 0x20u
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#define HDA_RING_SIZE_CAP_256 0x40u
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#define HDA_RING_SIZE_SELECT_2 0x00u
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#define HDA_RING_SIZE_SELECT_16 0x01u
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#define HDA_RING_SIZE_SELECT_256 0x02u
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#define HDA_DPLBASE_ENABLE 0x00000001u
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#define HDA_STREAM_REG_CTL 0x00u
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#define HDA_STREAM_REG_STS 0x03u
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#define HDA_STREAM_REG_LPIB 0x04u
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#define HDA_STREAM_REG_CBL 0x08u
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#define HDA_STREAM_REG_LVI 0x0Cu
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#define HDA_STREAM_REG_FORMAT 0x12u
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#define HDA_STREAM_REG_BDLPL 0x18u
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#define HDA_STREAM_REG_BDLPU 0x1Cu
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#define HDA_STREAM_CTL_RESET 0x000001u
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#define HDA_STREAM_CTL_RUN 0x000002u
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#define HDA_STREAM_CTL_INTERRUPT_COMPLETE 0x000004u
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#define HDA_STREAM_CTL_INTERRUPT_FIFO_ERROR 0x000008u
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#define HDA_STREAM_CTL_INTERRUPT_DESCRIPTOR_ERROR 0x000010u
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#define HDA_STREAM_CTL_INTERRUPT_MASK 0x00001Cu
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#define HDA_STREAM_CTL_TAG_SHIFT 20u
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#define HDA_STREAM_CTL_TAG_MASK 0x00F00000u
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#define HDA_STREAM_STS_COMPLETE 0x04u
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#define HDA_STREAM_STS_FIFO_ERROR 0x08u
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#define HDA_STREAM_STS_DESCRIPTOR_ERROR 0x10u
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#define HDA_STREAM_STS_ERROR_MASK 0x18u
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#define HDA_STREAM_STS_INTERRUPT_MASK 0x1Cu
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#define HDA_BDL_FLAG_INTERRUPT_ON_COMPLETION 0x00000001u
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#define HDA_VERB_GET_PARAMETER(parameterId) (0xF0000u | ((uint32_t)(parameterId) & 0xFFu))
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#define HDA_PARAMETER_VENDOR_ID 0x00u
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#define HDA_CONTROLLER_RESET_TIMEOUT_US 100000u
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#define HDA_STREAM_RESET_TIMEOUT_US 10000u
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#define HDA_RING_RESET_TIMEOUT_US 10000u
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#define HDA_CODEC_COMMAND_TIMEOUT_US 100000u
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#define HDA_CODEC_COMMAND_ATTEMPTS 2u
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#define HDA_CODEC_RESET_SETTLE_US 1000u
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#define HDA_STREAM_ERROR_WINDOW_US 1000000ull
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#define HDA_STREAM_ERRORS_BEFORE_CONTROLLER_RESET 3u
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#define HDA_RECOVERY_NONE 0u
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#define HDA_RECOVERY_STREAM 1u
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#define HDA_RECOVERY_CONTROLLER 2u
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#pragma pack(push, 1)
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typedef struct HDA_BDL_ENTRY {
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uint64_t Address;
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uint32_t Length;
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uint32_t Flags;
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} HDA_BDL_ENTRY;
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typedef struct HDA_RIRB_ENTRY {
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uint32_t Response;
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uint32_t ResponseExtra;
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} HDA_RIRB_ENTRY;
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#pragma pack(pop)
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_Static_assert(sizeof(HDA_BDL_ENTRY) == 16u, "HDA BDL entries must be 16 bytes");
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_Static_assert(sizeof(HDA_RIRB_ENTRY) == 8u, "HDA RIRB entries must be 8 bytes");
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typedef struct HDA_CONTROLLER HDA_CONTROLLER;
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typedef struct HDA_CODEC_STATE HDA_CODEC_STATE;
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typedef struct HDA_OUTPUT_DESCRIPTION {
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void* PeriodBuffer;
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size_t PeriodBufferBytes;
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uint32_t PeriodCount;
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uint32_t FramesPerPeriod;
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size_t PeriodStrideBytes;
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IO_AUDIO_FORMAT HardwareFormat;
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uint8_t StreamTag;
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} HDA_OUTPUT_DESCRIPTION;
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typedef struct HDA_TRANSPORT_CALLBACKS {
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// Reports one BDL-owned period after completion interrupt processing.
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void (*PeriodComplete)(void* context,
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uint32_t completedPeriodIndex,
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uint64_t presentedFrames,
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uint64_t finePositionFrames,
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uint64_t interruptCount,
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uint64_t timestampTicks);
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// Delivers one unsolicited codec response outside the controller lock.
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void (*UnsolicitedResponse)(void* context,
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uint8_t codecAddress,
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uint32_t response,
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uint32_t responseExtra);
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// Restores codec programming in a muted state while transport start and stop are serialized.
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KSTATUS (*RestoreAfterControllerReset)(void* context);
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// Unmutes the restored route only after controller recovery has restarted DMA.
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KSTATUS (*ResumeAfterControllerReset)(void* context);
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// Reports a recovery failure that leaves the transport stopped.
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void (*TransportFailure)(void* context, KSTATUS status);
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} HDA_TRANSPORT_CALLBACKS;
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typedef struct HDA_UNSOLICITED_RESPONSE {
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uint32_t Response;
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uint32_t ResponseExtra;
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} HDA_UNSOLICITED_RESPONSE;
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typedef struct HDA_OUTPUT_RING {
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IO_DMA_BUFFER* Dma;
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uint8_t* Buffer;
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uint64_t DeviceAddress;
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uint8_t NextLogicalPeriod;
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uint64_t PresentedFrames;
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} HDA_OUTPUT_RING;
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typedef struct HDA_OUTPUT_STREAM {
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uint8_t DescriptorIndex;
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uint8_t StreamTag;
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uint8_t BdlPeriodMap[HDA_OUTPUT_PERIOD_COUNT];
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uint8_t NextCompletionBdl;
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bool Prepared;
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bool Running;
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volatile int32_t PendingPeriodInterrupts;
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volatile int32_t PendingDmaErrors;
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HDA_OUTPUT_RING Rings[HDA_MAX_LOGICAL_ENDPOINTS];
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uint8_t ActiveRingIndex;
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IO_DMA_BUFFER* BdlDma;
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HDA_BDL_ENTRY* Bdl;
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uint64_t BdlDeviceAddress;
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uint64_t PositionRunBaseFrames;
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uint64_t LastPositionFrames;
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uint64_t PositionWrapFrames;
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uint32_t LastHardwarePositionBytes;
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bool PositionInitialized;
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uint64_t InterruptCount;
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uint64_t PeriodCompletionCount;
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uint64_t DmaErrorCount;
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uint64_t StreamResetCount;
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uint64_t PositionBufferReadCount;
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uint64_t LpibReadCount;
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uint64_t PositionDiscontinuityCount;
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} HDA_OUTPUT_STREAM;
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struct HDA_CONTROLLER {
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uint32_t Magic;
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DEVICE_OBJECT* Fdo;
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DEVICE_OBJECT* Pdo;
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DEVICE_OBJECT* LowerDevice;
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PCI_DEVICE_INFO PciInfo;
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volatile uint8_t* Registers;
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uint64_t RegisterBytes;
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uint16_t Gcap;
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uint8_t InputStreamCount;
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uint8_t OutputStreamCount;
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uint8_t BidirectionalStreamCount;
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uint8_t TotalStreamCount;
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uint16_t CodecMask;
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uint8_t Irq;
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bool UsingMsi;
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bool Started;
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bool Removed;
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bool SurpriseRemoved;
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SPINLOCK StateLock;
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KDPC Dpc;
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volatile int32_t IsrActive;
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volatile int32_t DpcActive;
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IO_DMA_ADAPTER* DmaAdapter;
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IO_DMA_BUFFER* CorbDma;
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IO_DMA_BUFFER* RirbDma;
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IO_DMA_BUFFER* PositionDma;
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uint32_t* Corb;
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HDA_RIRB_ENTRY* Rirb;
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volatile uint64_t* PositionBuffer;
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uint64_t CorbDeviceAddress;
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uint64_t RirbDeviceAddress;
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uint64_t PositionDeviceAddress;
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uint16_t CorbEntryCount;
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uint16_t RirbEntryCount;
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uint16_t CorbWritePointer;
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uint16_t RirbReadPointer;
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MUTEX* CommandMutex;
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MUTEX* StreamMutex;
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bool CommandWaiting;
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bool CommandResponseReady;
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uint8_t CommandCodecAddress;
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uint32_t CommandResponse;
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uint32_t CommandResponseExtra;
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uint64_t CodecCommandCount;
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uint64_t CodecCommandRetryCount;
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uint64_t CodecCommandFailureCount;
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uint64_t RirbResponseCount;
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uint64_t RirbUnsolicitedCount;
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uint64_t RirbOverrunCount;
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uint64_t CorbMemoryErrorCount;
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HDA_UNSOLICITED_RESPONSE Unsolicited[HDA_MAX_UNSOLICITED_RESPONSES];
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uint8_t UnsolicitedRead;
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uint8_t UnsolicitedWrite;
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uint8_t UnsolicitedCount;
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HDA_OUTPUT_STREAM Output;
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HDA_TRANSPORT_CALLBACKS Callbacks;
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void* CallbackContext;
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SEMAPHORE* RecoverySemaphore;
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EVENT* RecoveryFinished;
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THREAD* RecoveryThread;
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bool RecoveryWorkerRunning;
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bool RecoveryInProgress;
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uint8_t PendingRecovery;
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uint64_t StreamErrorWindowStart;
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uint32_t StreamErrorsInWindow;
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uint64_t ControllerResetCount;
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HDA_CODEC_STATE* Codec;
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uint64_t InterruptCount;
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uint64_t ControllerInterruptCount;
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};
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extern const NTL_DDK* gHdaDdk;
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// Returns one byte from the controller register aperture.
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uint8_t HdaRead8(const HDA_CONTROLLER* controller, uint32_t offset);
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// Returns one word from the controller register aperture.
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uint16_t HdaRead16(const HDA_CONTROLLER* controller, uint32_t offset);
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// Returns one dword from the controller register aperture.
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uint32_t HdaRead32(const HDA_CONTROLLER* controller, uint32_t offset);
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// Writes one byte to the controller register aperture.
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void HdaWrite8(HDA_CONTROLLER* controller, uint32_t offset, uint8_t value);
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// Writes one word to the controller register aperture.
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void HdaWrite16(HDA_CONTROLLER* controller, uint32_t offset, uint16_t value);
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// Writes one dword to the controller register aperture.
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void HdaWrite32(HDA_CONTROLLER* controller, uint32_t offset, uint32_t value);
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// Returns the register offset of the controller's one output stream descriptor.
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uint32_t HdaOutputStreamBase(const HDA_CONTROLLER* controller);
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// Allocates the transport and output DMA resources for one controller.
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KSTATUS HdaAllocateDma(HDA_CONTROLLER* controller);
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// Releases all DMA and synchronization resources owned by one controller.
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void HdaReleaseDma(HDA_CONTROLLER* controller);
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// Resets and initializes the controller, command rings, position buffer, and output descriptor.
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KSTATUS HdaInitializeController(HDA_CONTROLLER* controller);
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// Arms controller and output-stream interrupts after ISR registration.
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void HdaArmInterrupts(HDA_CONTROLLER* controller);
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// Stops hardware access without releasing software resources.
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void HdaQuiesceController(HDA_CONTROLLER* controller);
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// Sends one 20-bit codec verb payload through CORB/RIRB with one retry.
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KSTATUS HdaCodecVerb(HDA_CONTROLLER* controller,
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uint8_t codecAddress,
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uint8_t nodeId,
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uint32_t verbPayload,
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uint32_t* responseOut);
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// Copies one logical endpoint ring contract for codec and endpoint setup.
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KSTATUS HdaDescribeOutput(HDA_CONTROLLER* controller,
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uint8_t ringIndex,
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HDA_OUTPUT_DESCRIPTION* descriptionOut);
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// Selects one logical endpoint ring while the stream is stopped.
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KSTATUS HdaSelectOutputRing(HDA_CONTROLLER* controller, uint8_t ringIndex);
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// Replaces the transport callbacks while the output stream is stopped.
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KSTATUS HdaSetTransportCallbacks(HDA_CONTROLLER* controller,
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const HDA_TRANSPORT_CALLBACKS* callbacks,
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void* context);
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// Starts the prepared fixed-format output stream.
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KSTATUS HdaStartOutput(HDA_CONTROLLER* controller);
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// Stops the output stream while retaining its DMA ring.
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void HdaStopOutput(HDA_CONTROLLER* controller);
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// Returns the monotonic fine position derived from the position buffer or LPIB.
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uint64_t HdaQueryOutputPositionFrames(HDA_CONTROLLER* controller);
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// Captures one controller interrupt and queues deferred processing.
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void HdaHandleInterrupt(HDA_CONTROLLER* controller);
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// Runs period delivery, unsolicited callbacks, and recovery scheduling at DPC level.
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void HdaDpcRoutine(KDPC* dpc, void* context, void* systemArgument1, void* systemArgument2);
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// Starts the passive recovery worker for one controller.
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KSTATUS HdaStartRecoveryWorker(HDA_CONTROLLER* controller);
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// Stops and joins the passive recovery worker for one controller.
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void HdaStopRecoveryWorker(HDA_CONTROLLER* controller);
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// Discovers codec topology and registers usable analog render endpoints.
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KSTATUS HdaCodecInitialize(HDA_CONTROLLER* controller);
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// Stops jack workers and unregisters codec endpoints.
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void HdaCodecStop(HDA_CONTROLLER* controller, IO_AUDIO_REMOVAL_MODE mode);
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// Releases codec topology storage after interrupt work is quiescent.
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void HdaCodecDestroy(HDA_CONTROLLER* controller);
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