666 lines
25 KiB
C
666 lines
25 KiB
C
// ahci.c - AHCI disk command path and DriverEntry.
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#include "ahci.h"
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const HAL_API *g_hal;
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HBA_MEM *g_hba;
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uint8_t g_irq;
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DRIVER_OBJECT g_driver;
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AHCI_DRIVE g_drives[MAX_AHCI_DRIVES];
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int g_driveCount;
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// ---------------------------------------------------------------------------
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// Helpers
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// ---------------------------------------------------------------------------
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// Accessors for port structure memory at known offsets from structVirt/Phys
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static inline HBA_CMD_HEADER *cmd_list(AHCI_DRIVE *drv) {
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return (HBA_CMD_HEADER *)((uint8_t *)drv->structVirt + PORT_OFF_CMDLIST);
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}
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static inline uint64_t cmd_list_phys(AHCI_DRIVE *drv) {
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return drv->structPhys + PORT_OFF_CMDLIST;
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}
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static inline uint64_t fis_phys(AHCI_DRIVE *drv) {
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return drv->structPhys + PORT_OFF_FIS;
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}
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static inline HBA_CMD_TBL *cmd_tbl(AHCI_DRIVE *drv, int slot) {
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return (HBA_CMD_TBL *)((uint8_t *)drv->structVirt
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+ PORT_OFF_CMDTBLS
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+ (uint32_t)slot * PORT_CMDTBL_SIZE);
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}
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static inline uint64_t cmd_tbl_phys(AHCI_DRIVE *drv, int slot) {
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return drv->structPhys + PORT_OFF_CMDTBLS
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+ (uint64_t)slot * PORT_CMDTBL_SIZE;
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}
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// ---------------------------------------------------------------------------
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// Port engine start / stop (polling safe)
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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// Port memory initialisation
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// ---------------------------------------------------------------------------
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static KSTATUS port_init_memory(AHCI_DRIVE *drv) {
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uint64_t flags = PAGE_PRESENT | PAGE_WRITE | PAGE_NOCACHE;
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drv->structPhys = MmAllocateContiguous(PORT_PAGES_STRUCT);
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if (!drv->structPhys) return STATUS_NO_MEMORY;
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drv->structVirt = g_hal->PhysToVirt(drv->structPhys);
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// Force NOCACHE on DMA descriptor memory
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MmSetPageProtect((uintptr_t)drv->structVirt,
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PORT_PAGES_STRUCT * 4096, flags);
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memset(drv->structVirt, 0, PORT_PAGES_STRUCT * 4096);
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drv->bouncePhys = MmAllocateContiguous(BOUNCE_PAGES);
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if (!drv->bouncePhys) return STATUS_NO_MEMORY;
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drv->bounceVirt = g_hal->PhysToVirt(drv->bouncePhys);
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// Bounce buffer: NOCACHE to ensure CPU writes reach physical memory
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// before the HBA's DMA engine reads them
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MmSetPageProtect((uintptr_t)drv->bounceVirt,
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BOUNCE_PAGES * 4096, flags);
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memset(drv->bounceVirt, 0, BOUNCE_BYTES);
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HBA_PORT *port = drv->port;
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port_stop(port);
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// Set command list base
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port->clb = (uint32_t)(cmd_list_phys(drv) & 0xFFFFFFFF);
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port->clbu = (uint32_t)(cmd_list_phys(drv) >> 32);
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// Set FIS base
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port->fb = (uint32_t)(fis_phys(drv) & 0xFFFFFFFF);
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port->fbu = (uint32_t)(fis_phys(drv) >> 32);
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// Initialise all 32 command headers, pointing each to its command table
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HBA_CMD_HEADER *hdrs = cmd_list(drv);
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for (int i = 0; i < NUM_CMD_SLOTS; i++) {
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hdrs[i].prdtl = PORT_PRDT_COUNT;
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uint64_t tbl = cmd_tbl_phys(drv, i);
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hdrs[i].ctba = (uint32_t)(tbl & 0xFFFFFFFF);
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hdrs[i].ctbau = (uint32_t)(tbl >> 32);
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}
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// Clear any stale interrupts then start the port engine
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port->serr = (uint32_t)-1;
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port->is = (uint32_t)-1;
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port_start(port);
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return STATUS_SUCCESS;
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}
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// ---------------------------------------------------------------------------
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// Issue a command - polling fallback (used during early init / IDENTIFY only,
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// before the scheduler and interrupt handler are live).
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// Returns STATUS_SUCCESS, STATUS_DEVICE_ERROR, or STATUS_TIMEOUT.
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// ---------------------------------------------------------------------------
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static KSTATUS port_issue_cmd_poll(AHCI_DRIVE *drv) {
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HBA_PORT *port = drv->port;
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// Clear pending interrupts before issuing
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port->is = (uint32_t)-1;
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// Wait for port to be idle (not BSY or DRQ)
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int spin = 0;
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while ((port->tfd & (ATA_SR_BUSY | ATA_SR_DRQ)) && spin < POLL_TIMEOUT)
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spin++;
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if (spin == POLL_TIMEOUT) {
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DbgPrint("AHCI: port hung (pre-issue)\n");
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return STATUS_TIMEOUT;
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}
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// Issue slot 0
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port->ci = (1u << 0);
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// Poll until slot 0 clears
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while (true) {
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if (!(port->ci & (1u << 0))) break;
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if (port->is & (PORT_IS_TFES | PORT_IS_HBFS | PORT_IS_HBDS | PORT_IS_IFS)) {
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DbgPrint("AHCI: error IS=0x%x TFD=0x%x SERR=0x%x\n",
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port->is, port->tfd, port->serr);
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port->serr = (uint32_t)-1;
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port->is = (uint32_t)-1;
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return STATUS_DEVICE_ERROR;
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}
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}
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if (port->is & PORT_IS_TFES) {
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DbgPrint("AHCI: TFES after completion TFD=0x%x\n", port->tfd);
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port->is = (uint32_t)-1;
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return STATUS_DEVICE_ERROR;
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}
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return STATUS_SUCCESS;
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}
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// ---------------------------------------------------------------------------
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// Interrupt bottom half. The ISR owns hardware acknowledgement and status
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// capture; this DPC wakes the worker thread after the hard IRQ has unwound.
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// ---------------------------------------------------------------------------
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static void AhciCompletionDpc(KDPC *dpc, void *context,
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void *systemArgument1, void *systemArgument2) {
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(void)dpc;
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(void)systemArgument1;
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(void)systemArgument2;
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AHCI_DRIVE *drv = (AHCI_DRIVE *)context;
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if (drv && drv->completionEvent)
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KeSignalEvent(drv->completionEvent);
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}
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// ---------------------------------------------------------------------------
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// ISR - called from KeIrqDispatch on the AHCI PCI IRQ line.
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// Walks all registered drives, checks if their port raised an interrupt,
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// captures IS, clears it, and queues the per-drive completion DPC.
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// ---------------------------------------------------------------------------
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static void AhciIsr(void) {
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if (!g_hba) return;
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// GHC.IS tells us which ports are pending.
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uint32_t pending = g_hba->is;
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if (!pending) return;
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for (int i = 0; i < g_driveCount; i++) {
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AHCI_DRIVE *drv = &g_drives[i];
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uint32_t portBit = (1u << drv->portNo);
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if (!(pending & portBit)) continue;
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// Capture and clear port IS before queueing the bottom half. The
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// waiter reads lastIs to check for errors without racing the next
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// command. OR in case hardware reports multiple causes before the
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// DPC releases the worker.
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uint32_t portIs = drv->port->is;
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drv->port->is = portIs; // W1C - write back to clear
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drv->lastIs |= portIs;
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// Clear the HBA-level bit.
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g_hba->is = portBit;
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KeInsertQueueDpc(&drv->completionDpc, (void *)0, (void *)0);
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}
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}
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// ---------------------------------------------------------------------------
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// Issue a command - interrupt-driven (runtime path).
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// Caller has already built slot 0 via build_rw_cmd / port_identify.
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// Blocks the current thread until the ISR signals completionEvent.
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// ---------------------------------------------------------------------------
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static KSTATUS port_issue_cmd(AHCI_DRIVE *drv) {
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HBA_PORT *port = drv->port;
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// Clear stale IS and snapshot before issuing so we don't mis-read a
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// leftover value from a prior command.
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port->is = (uint32_t)-1;
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drv->lastIs = 0;
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// Wait for port idle
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int spin = 0;
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while ((port->tfd & (ATA_SR_BUSY | ATA_SR_DRQ)) && spin < POLL_TIMEOUT)
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spin++;
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if (spin == POLL_TIMEOUT) {
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DbgPrint("AHCI: port hung (pre-issue)\n");
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return STATUS_TIMEOUT;
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}
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// Issue slot 0, then block on the event.
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port->ci = (1u << 0);
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KeWaitForEvent(drv->completionEvent, 0);
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// The ISR has cleared IS - check for errors in the snapshot.
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uint32_t is = drv->lastIs;
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if (is & (PORT_IS_TFES | PORT_IS_HBFS | PORT_IS_HBDS | PORT_IS_IFS)) {
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DbgPrint("AHCI: error IS=0x%x TFD=0x%x SERR=0x%x\n",
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is, port->tfd, port->serr);
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port->serr = (uint32_t)-1;
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return STATUS_DEVICE_ERROR;
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}
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return STATUS_SUCCESS;
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}
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// ---------------------------------------------------------------------------
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// Build a standard DMA read or write command in slot 0
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// ---------------------------------------------------------------------------
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static void build_rw_cmd(AHCI_DRIVE *drv, uint64_t lba, uint32_t sectors,
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uint64_t bufPhys, bool write) {
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HBA_CMD_HEADER *hdr = cmd_list(drv); // slot 0
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HBA_CMD_TBL *tbl = cmd_tbl(drv, 0);
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memset(tbl, 0, PORT_CMDTBL_SIZE);
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// How many PRDT entries we need (each covers up to 8K = 16 sectors)
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uint32_t prdtl = (sectors + 15) / 16;
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if (prdtl > PORT_PRDT_COUNT) prdtl = PORT_PRDT_COUNT; // capped (see caller)
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hdr->cfl = sizeof(FIS_REG_H2D) / 4;
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hdr->w = write ? 1 : 0;
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hdr->prdtl = (uint16_t)prdtl;
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hdr->prdbc = 0;
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// Fill PRDT entries
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uint32_t remaining = sectors;
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uint64_t buf = bufPhys;
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for (uint32_t i = 0; i < prdtl; i++) {
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uint32_t sects = (remaining > 16) ? 16 : remaining;
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uint32_t bytes = sects * 512;
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tbl->prdt_entry[i].dba = (uint32_t)(buf & 0xFFFFFFFF);
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tbl->prdt_entry[i].dbau = (uint32_t)(buf >> 32);
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tbl->prdt_entry[i].dbc = bytes - 1; // hardware adds 1
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tbl->prdt_entry[i].i = (i == prdtl - 1) ? 1 : 0;
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buf += bytes;
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remaining -= sects;
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}
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// Build H2D FIS
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FIS_REG_H2D *fis = (FIS_REG_H2D *)tbl->cfis;
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memset(fis, 0, sizeof(*fis));
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fis->fis_type = FIS_TYPE_REG_H2D;
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fis->c = 1;
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fis->command = write ? ATA_CMD_WRITE_DMA_EX : ATA_CMD_READ_DMA_EX;
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fis->device = 1u << 6; // LBA mode
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fis->lba0 = (uint8_t)(lba);
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fis->lba1 = (uint8_t)(lba >> 8);
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fis->lba2 = (uint8_t)(lba >> 16);
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fis->lba3 = (uint8_t)(lba >> 24);
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fis->lba4 = (uint8_t)(lba >> 32);
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fis->lba5 = (uint8_t)(lba >> 40);
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fis->countl = (uint8_t)(sectors & 0xFF);
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fis->counth = (uint8_t)(sectors >> 8);
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}
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// ---------------------------------------------------------------------------
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// IDENTIFY command - fills a 512-byte buffer and returns it
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// ---------------------------------------------------------------------------
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static KSTATUS port_identify(AHCI_DRIVE *drv) {
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// Reuse bounce buffer for IDENTIFY data (512 bytes)
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memset(drv->bounceVirt, 0, 512);
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HBA_CMD_HEADER *hdr = cmd_list(drv);
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HBA_CMD_TBL *tbl = cmd_tbl(drv, 0);
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memset(tbl, 0, PORT_CMDTBL_SIZE);
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hdr->cfl = sizeof(FIS_REG_H2D) / 4;
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hdr->w = 0;
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hdr->prdtl = 1;
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hdr->prdbc = 0;
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tbl->prdt_entry[0].dba = (uint32_t)(drv->bouncePhys & 0xFFFFFFFF);
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tbl->prdt_entry[0].dbau = (uint32_t)(drv->bouncePhys >> 32);
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tbl->prdt_entry[0].dbc = 512 - 1;
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tbl->prdt_entry[0].i = 1;
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FIS_REG_H2D *fis = (FIS_REG_H2D *)tbl->cfis;
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memset(fis, 0, sizeof(*fis));
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fis->fis_type = FIS_TYPE_REG_H2D;
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fis->c = 1;
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fis->command = ATA_CMD_IDENTIFY;
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fis->device = 0;
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// Poll: IDENTIFY runs before the scheduler and IRQ handler are live.
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KSTATUS st = port_issue_cmd_poll(drv);
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if (!KSUCCESS(st)) return st;
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// Parse sector count from IDENTIFY data
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const uint16_t *id = (const uint16_t *)drv->bounceVirt;
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if (id[ATA_IDENT_W83] & (1u << 10)) {
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// 48-bit LBA supported
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drv->sectorCount = (uint64_t)id[ATA_IDENT_W100]
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| ((uint64_t)id[ATA_IDENT_W100 + 1] << 16)
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| ((uint64_t)id[ATA_IDENT_W100 + 2] << 32)
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| ((uint64_t)id[ATA_IDENT_W100 + 3] << 48);
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} else {
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// 28-bit LBA
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drv->sectorCount = (uint64_t)id[ATA_IDENT_W60]
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| ((uint64_t)id[ATA_IDENT_W60 + 1] << 16);
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}
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return STATUS_SUCCESS;
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}
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// Core read logic
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static KSTATUS do_read(AHCI_DRIVE *drv, uint64_t lba,
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uint32_t count, void *buf) {
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uint8_t *out = (uint8_t *)buf;
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while (count > 0) {
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uint32_t batch = (count > BOUNCE_SECTORS) ? BOUNCE_SECTORS : count;
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build_rw_cmd(drv, lba, batch, drv->bouncePhys, false);
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KSTATUS st = port_issue_cmd(drv);
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if (!KSUCCESS(st)) return st;
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memcpy(out, drv->bounceVirt, (size_t)batch * 512);
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out += (size_t)batch * 512;
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lba += batch;
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count -= batch;
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}
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return STATUS_SUCCESS;
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}
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// Core write logic
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static KSTATUS do_write(AHCI_DRIVE *drv, uint64_t lba,
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uint32_t count, const void *buf) {
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const uint8_t *in = (const uint8_t *)buf;
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while (count > 0) {
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uint32_t batch = (count > BOUNCE_SECTORS) ? BOUNCE_SECTORS : count;
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memcpy(drv->bounceVirt, in, (size_t)batch * 512);
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build_rw_cmd(drv, lba, batch, drv->bouncePhys, true);
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KSTATUS st = port_issue_cmd(drv);
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if (!KSUCCESS(st)) return st;
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in += (size_t)batch * 512;
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lba += batch;
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count -= batch;
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}
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return STATUS_SUCCESS;
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}
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// ---------------------------------------------------------------------------
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// Async IRP dispatch
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// ---------------------------------------------------------------------------
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// AhciDispatchReadWrite - DEVICE_OBJECT dispatch entry for disk IRPs.
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// Accepted IRPs are queued to the per-drive worker and completed later with
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// IoCompleteRequest(). Rejected IRPs are returned synchronously and are not
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// completed.
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static KSTATUS AhciDispatchReadWrite(DEVICE_OBJECT *device, IRP *irp) {
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if (!device || !irp) return STATUS_INVALID_PARAMETER;
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AHCI_DRIVE *drv = (AHCI_DRIVE *)device->DeviceExtension;
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if (!drv) return STATUS_INVALID_PARAMETER;
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if (irp->SectorCount == 0 || !irp->Buffer) return STATUS_INVALID_PARAMETER;
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if (irp->Lba + irp->SectorCount > drv->sectorCount) return STATUS_INVALID_PARAMETER;
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irp->Status = STATUS_FAILURE;
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irp->Information = 0;
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IrpQueueEnqueue(&drv->irpQueue, irp);
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return STATUS_PENDING;
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}
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// AhciWorker - kernel thread, one per drive.
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// Dequeues IRPs and executes them one at a time using the existing
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// single-slot interrupt-driven path. Completion fires the IRP's event
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// and/or callback so the original caller can observe the result without
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// ever having blocked in a driver call.
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//
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// NCQ TODO: replace the serialised loop with a multi-slot dispatcher:
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// 1. KeWaitSemaphore() to wait for a free slot AND a pending IRP.
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// 2. Pick the oldest IRP from the queue.
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// 3. Grab a free bit in drv->slotMask (under the slot spinlock).
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// 4. Copy write data into slotBounce[slot], build the NCQ FIS (FPDMA),
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// record slotIrp[slot] = irp, and issue via port->sact + port->ci.
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// 5. Return immediately - the ISR drives all completions.
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static void AhciWorker(uintptr_t arg) {
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AHCI_DRIVE *drv = (AHCI_DRIVE *)arg;
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while (true) {
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// Block until AHCI dispatch signals a new IRP.
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KeWaitSemaphore(drv->irpQueue.Semaphore);
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IRP *irp = IrpQueueDequeue(&drv->irpQueue);
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if (!irp) KePanic(KE_PANIC_CODE_DRIVER, "AhciWorker: semaphore fired but queue is empty - IRP accounting bug\n");
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bool write = !!(irp->Flags & IRP_FLAG_WRITE);
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KSTATUS st;
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if (write)
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st = do_write(drv, irp->Lba, irp->SectorCount, irp->Buffer);
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else
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st = do_read (drv, irp->Lba, irp->SectorCount, irp->Buffer);
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// Publish result then fire completion hooks through the common I/O path.
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IoCompleteRequest(irp, st, KSUCCESS(st) ? ((size_t)irp->SectorCount * 512u) : 0);
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}
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}
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// ---------------------------------------------------------------------------
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// AHCI controller initialisation
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// ---------------------------------------------------------------------------
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// Before memory init: only check physical link. Signature is not yet valid.
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// After COMRESET + FIS receive: check signature for SATA disk.
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// Issue a COMRESET on the port, wait for link re-establishment and D2H FIS.
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// FRE must already be set (port_init_memory does this) so the HBA can
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// capture the signature FIS the device sends after the reset.
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// PORT_IE bits we care about:
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// DHRS (bit 0) - D2H Register FIS received - normal completion
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// PSS (bit 1) - PIO Setup FIS received
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// DSS (bit 2) - DMA Setup FIS received
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// SDBS (bit 3) - Set Device Bits FIS received
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// TFES (bit 30) - Task File Error Status - error
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// HBFS (bit 29) - Host Bus Fatal error
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// HBDS (bit 28) - Host Bus Data error
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// IFS (bit 27) - Interface Fatal error
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#define PORT_IE_NORMAL (0x0000000Fu)
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#define PORT_IE_ERRORS (PORT_IS_TFES | PORT_IS_HBFS | PORT_IS_HBDS | PORT_IS_IFS)
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#define PORT_IE_ALL (PORT_IE_NORMAL | PORT_IE_ERRORS)
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KSTATUS AhciInitialize(const HAL_API *hal) {
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g_hal = hal;
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g_driveCount = 0;
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memset(&g_driver, 0, sizeof(g_driver));
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g_driver.Name = "ahci";
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g_driver.MajorFunction[IRP_MJ_READ] = AhciDispatchReadWrite;
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g_driver.MajorFunction[IRP_MJ_WRITE] = AhciDispatchReadWrite;
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// -----------------------------------------------------------------------
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// Locate AHCI controller via PCI class scan
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// -----------------------------------------------------------------------
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uint8_t pciBus, pciDev, pciFn;
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if (!hal->Pci.FindClass(PCI_AHCI_CLASS, PCI_AHCI_SUBCLASS,
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&pciBus, &pciDev, &pciFn)) {
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DbgPrint("AHCI: no AHCI controller found\n");
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return STATUS_NOT_FOUND;
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}
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DbgPrint("AHCI: controller at PCI %02x:%02x.%x\n", pciBus, pciDev, pciFn);
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// -----------------------------------------------------------------------
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// Enable Bus Master + Memory Space in PCI command register
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// -----------------------------------------------------------------------
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uint32_t cmd = hal->Pci.Read32(pciBus, pciDev, pciFn, PCI_CMD_REG);
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cmd |= (PCI_CMD_BUSMASTER | PCI_CMD_MEMSPACE); cmd &= ~(1 << 10); cmd |= (1 << 2);
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hal->Pci.Write32(pciBus, pciDev, pciFn, PCI_CMD_REG, cmd);
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// -----------------------------------------------------------------------
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// Read PCI IRQ line
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// -----------------------------------------------------------------------
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g_irq = hal->Pci.GetIrqLine(pciBus, pciDev, pciFn);
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if (g_irq == 0xFF) {
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DbgPrint("AHCI: no PCI IRQ wired - cannot use interrupt-driven mode\n");
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return STATUS_NOT_SUPPORTED;
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}
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DbgPrint("AHCI: PCI IRQ line = %u\n", (unsigned)g_irq);
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// -----------------------------------------------------------------------
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// Read ABAR (BAR5) and map as uncacheable
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// -----------------------------------------------------------------------
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uint32_t bar5 = hal->Pci.Read32(pciBus, pciDev, pciFn, PCI_BAR5_REG);
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uint64_t abarPhys = (uint64_t)(bar5 & ~0xFFFu);
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KSTATUS st = ahci_map_mmio(abarPhys);
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if (!KSUCCESS(st)) return st;
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g_hba = (HBA_MEM *)hal->PhysToVirt(abarPhys);
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DbgPrint("AHCI: ABAR phys=0x%016llX version=0x%08x\n",
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(unsigned long long)abarPhys, g_hba->vs);
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// -----------------------------------------------------------------------
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// HBA reset + BIOS handoff (also enables GHC.IE)
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// -----------------------------------------------------------------------
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st = hba_reset(g_hba);
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if (!KSUCCESS(st)) return st;
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// -----------------------------------------------------------------------
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// Log capability summary
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// -----------------------------------------------------------------------
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uint32_t cap = g_hba->cap;
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uint32_t nPorts = (cap & 0x1F) + 1;
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uint32_t nSlots = ((cap >> 8) & 0x1F) + 1;
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bool s64a = !!(cap & (1u << 31));
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DbgPrint("AHCI: cap=0x%08x ports=%u slots=%u 64bit=%d\n",
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cap, nPorts, nSlots, (int)s64a);
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// -----------------------------------------------------------------------
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// Enumerate implemented ports
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// -----------------------------------------------------------------------
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uint32_t pi = g_hba->pi;
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for (uint32_t portno = 0; portno < 32 && g_driveCount < MAX_AHCI_DRIVES; portno++) {
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if (!(pi & (1u << portno))) continue;
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HBA_PORT *port = &g_hba->ports[portno];
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// Phase 1: physical link check
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if (!port_link_up(port)) {
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DbgPrint("AHCI: port %u: no link (ssts=0x%08x)\n", portno, port->ssts);
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continue;
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}
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DbgPrint("AHCI: port %u: link up, initializing...\n", portno);
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int driveIdx = g_driveCount;
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AHCI_DRIVE *drv = &g_drives[driveIdx];
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memset(drv, 0, sizeof(*drv));
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drv->port = port;
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drv->portNo = (uint8_t)portno;
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// Phase 2: allocate command list, FIS buffer, bounce buffer
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st = port_init_memory(drv);
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if (!KSUCCESS(st)) {
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DbgPrint("AHCI: port %u: memory init failed (0x%x)\n", portno, st);
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continue;
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}
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// Phase 3: COMRESET - forces device to re-send D2H FIS for valid SIG
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st = port_comreset(drv);
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if (!KSUCCESS(st)) {
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DbgPrint("AHCI: port %u: COMRESET failed\n", portno);
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continue;
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}
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// Phase 4: filter to SATA disks
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if (!port_is_sata_disk(port)) {
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DbgPrint("AHCI: port %u: not a SATA disk (sig=0x%08x), skipping\n",
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portno, port->sig);
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continue;
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}
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// Phase 5: create per-drive completion event (auto-reset, initially clear)
|
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st = KeEventCreate(EventAutoReset, 0, &drv->completionEvent);
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if (!KSUCCESS(st)) {
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DbgPrint("AHCI: port %u: event create failed (0x%x)\n", portno, st);
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continue;
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}
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KeInitializeDpc(&drv->completionDpc, AhciCompletionDpc, drv);
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// Phase 5b: create the IRP queue semaphore and initialise the queue.
|
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// The semaphore starts at 0; each submitted IRP increments it by one.
|
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SEMAPHORE *irpSem = (SEMAPHORE *)0;
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st = KeSemaphoreCreate(0, 0x7FFFFFFF, &irpSem);
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if (!KSUCCESS(st)) {
|
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DbgPrint("AHCI: port %u: semaphore create failed (0x%x)\n", portno, st);
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continue;
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}
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IrpQueueInit(&drv->irpQueue, irpSem);
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|
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// Phase 6: IDENTIFY (polled - scheduler not yet running)
|
|
st = port_identify(drv);
|
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if (!KSUCCESS(st)) {
|
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DbgPrint("AHCI: port %u: IDENTIFY failed (0x%x)\n", portno, st);
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continue;
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}
|
|
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DbgPrint("AHCI: drive %d: %llu sectors (%llu MB)\n",
|
|
driveIdx,
|
|
(unsigned long long)drv->sectorCount,
|
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(unsigned long long)(drv->sectorCount / 2048));
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// Phase 7: enable per-port interrupts.
|
|
// Clear any stale IS first so we don't get a spurious signal immediately.
|
|
port->is = (uint32_t)-1;
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|
port->ie = PORT_IE_ALL;
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// Phase 8: create and register a disk DEVICE_OBJECT.
|
|
st = IoCreateDevice(&g_driver, 0, &drv->deviceObject);
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|
if (!KSUCCESS(st)) {
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DbgPrint("AHCI: drive %d: IoCreateDevice failed (0x%x)\n", driveIdx, st);
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|
continue;
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}
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|
drv->deviceObject->DeviceExtension = drv;
|
|
drv->deviceObject->SectorCount = drv->sectorCount;
|
|
drv->deviceObject->AlignmentRequirement = 512;
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|
|
|
st = IoRegisterDiskDevice((uint8_t)driveIdx, drv->deviceObject);
|
|
if (KSUCCESS(st)) {
|
|
DbgPrint("AHCI: drive %d registered\n", driveIdx);
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|
g_driveCount++;
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|
} else {
|
|
DbgPrint("AHCI: IoRegisterDiskDevice(%d) failed (0x%x)\n", driveIdx, st);
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|
IoDeleteDevice(drv->deviceObject);
|
|
drv->deviceObject = (DEVICE_OBJECT*)0;
|
|
continue;
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|
}
|
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|
|
// Phase 9: spawn the per-drive IRP worker thread.
|
|
// The worker owns do_read / do_write exclusively once the scheduler
|
|
// is live; it is the only thread that may call port_issue_cmd().
|
|
st = KeCreateKernelThread((uintptr_t)AhciWorker, (uintptr_t)drv,
|
|
PriorityHigh, &drv->workerThread);
|
|
if (!KSUCCESS(st)) {
|
|
DbgPrint("AHCI: drive %d: worker thread create failed (0x%x)\n",
|
|
driveIdx, st);
|
|
// Fatal for this device: all disk access is IRP-based now, so
|
|
// leave the device registered but clearly fail during testing.
|
|
}
|
|
}
|
|
|
|
if (g_driveCount == 0) {
|
|
DbgPrint("AHCI: no drives found\n");
|
|
return STATUS_NOT_FOUND;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
// Register the ISR. All ports on this HBA share one PCI IRQ line.
|
|
// Do this after all drives are initialised so the ISR sees valid state.
|
|
// -----------------------------------------------------------------------
|
|
KeIrqRegister(g_irq, AhciIsr);
|
|
DbgPrint("AHCI: ISR registered on IRQ %u; initialised %d drive(s)\n",
|
|
(unsigned)g_irq, g_driveCount);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
KSTATUS DriverEntry(const HAL_API *hal) {
|
|
DbgPrint("AHCI: driver loading...\n");
|
|
KSTATUS st = AhciInitialize(hal);
|
|
if (!KSUCCESS(st))
|
|
DbgPrint("AHCI: init failed: 0x%x\n", st);
|
|
return st;
|
|
}
|