594 lines
22 KiB
C
594 lines
22 KiB
C
// usb.h - internal USB/xHCI driver interfaces shared across usb.sys translation units.
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#pragma once
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <string.h>
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#include <intrin.h>
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#include <ntlite/ddi/hal_api.h>
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#include <ntlite/ddi/input_device.h>
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#include <ntlite/ddi/io_driver.h>
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#include <ntlite/status.h>
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#include <kernel/ke_debug.h>
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#include <kernel/ke_irq.h>
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#include <kernel/ke_dpc.h>
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#include <kernel/ke_irp.h>
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#include <kernel/ke_spinlock.h>
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#include <kernel/mm_phys.h>
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#include <kernel/mm_virt.h>
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#ifndef USB_DEBUG_VERBOSE
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#define USB_DEBUG_VERBOSE 0
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#endif
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#if USB_DEBUG_VERBOSE
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#define UsbTrace DbgPrint
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#else
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static __inline void UsbTrace(const char* fmt, ...) { (void)fmt; }
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#endif
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#define PCI_VENDOR_INVALID 0xFFFFu
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#define PCI_CLASS_SERIAL_BUS 0x0Cu
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#define PCI_SUBCLASS_USB 0x03u
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#define PCI_PROGIF_XHCI 0x30u
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#define PCI_REG_VENDOR_DEVICE 0x00u
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#define PCI_REG_COMMAND 0x04u
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#define PCI_REG_CLASS 0x08u
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#define PCI_REG_BAR0 0x10u
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#define PCI_COMMAND_MEMORY (1u << 1)
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#define PCI_COMMAND_MASTER (1u << 2)
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#define PCI_COMMAND_INTX_DISABLE (1u << 10)
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#define XHCI_CAP_CAPLENGTH 0x00u
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#define XHCI_CAP_HCSPARAMS1 0x04u
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#define XHCI_CAP_HCSPARAMS2 0x08u
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#define XHCI_CAP_HCCPARAMS1 0x10u
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#define XHCI_CAP_DBOFF 0x14u
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#define XHCI_CAP_RTSOFF 0x18u
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#define XHCI_OP_USBCMD 0x00u
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#define XHCI_OP_USBSTS 0x04u
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#define XHCI_OP_PAGESIZE 0x08u
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#define XHCI_OP_DNCTRL 0x14u
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#define XHCI_OP_CRCR 0x18u
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#define XHCI_OP_DCBAAP 0x30u
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#define XHCI_OP_CONFIG 0x38u
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#define XHCI_OP_PORT_BASE 0x400u
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#define XHCI_OP_PORT_STRIDE 0x10u
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#define XHCI_USBCMD_RS (1u << 0)
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#define XHCI_USBCMD_HCRST (1u << 1)
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#define XHCI_USBCMD_INTE (1u << 2)
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#define XHCI_USBCMD_HSEE (1u << 3)
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#define XHCI_USBSTS_HCH (1u << 0)
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#define XHCI_USBSTS_HSE (1u << 2)
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#define XHCI_USBSTS_EINT (1u << 3)
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#define XHCI_USBSTS_PCD (1u << 4)
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#define XHCI_USBSTS_CNR (1u << 11)
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#define XHCI_USBSTS_HCE (1u << 12)
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#define XHCI_USBSTS_CLEAR_MASK (XHCI_USBSTS_HSE | XHCI_USBSTS_EINT | \
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XHCI_USBSTS_PCD | XHCI_USBSTS_HCE)
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#define XHCI_IMAN_IP (1u << 0)
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#define XHCI_IMAN_IE (1u << 1)
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#define XHCI_PORTSC_CCS (1u << 0)
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#define XHCI_PORTSC_PED (1u << 1)
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#define XHCI_PORTSC_OCA (1u << 3)
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#define XHCI_PORTSC_PR (1u << 4)
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#define XHCI_PORTSC_PP (1u << 9)
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#define XHCI_PORTSC_SPEED_SHIFT 10u
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#define XHCI_PORTSC_SPEED_MASK (0xFu << XHCI_PORTSC_SPEED_SHIFT)
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#define XHCI_PORTSC_CSC (1u << 17)
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#define XHCI_PORTSC_PEC (1u << 18)
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#define XHCI_PORTSC_WRC (1u << 19)
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#define XHCI_PORTSC_OCC (1u << 20)
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#define XHCI_PORTSC_PRC (1u << 21)
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#define XHCI_PORTSC_PLC (1u << 22)
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#define XHCI_PORTSC_CEC (1u << 23)
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#define XHCI_PORTSC_CHANGE_MASK (XHCI_PORTSC_CSC | XHCI_PORTSC_PEC | \
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XHCI_PORTSC_WRC | XHCI_PORTSC_OCC | \
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XHCI_PORTSC_PRC | XHCI_PORTSC_PLC | \
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XHCI_PORTSC_CEC)
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#define XHCI_EXT_CAP_LEGACY 0x01u
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#define XHCI_EXT_CAP_PROTOCOL 0x02u
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#define XHCI_LEGSUP_BIOS_OWNED (1u << 16)
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#define XHCI_LEGSUP_OS_OWNED (1u << 24)
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#define XHCI_TRB_TYPE_SHIFT 10u
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#define XHCI_TRB_TYPE_MASK 0x3Fu
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#define XHCI_TRB_CYCLE (1u << 0)
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#define XHCI_TRB_LINK_TC (1u << 1)
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#define XHCI_TRB_TYPE_LINK 6u
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#define XHCI_TRB_TYPE_NOOP_CMD 23u
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#define XHCI_TRB_TYPE_CMD_DONE 33u
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#define XHCI_TRB_TYPE_PORT_SC 34u
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#define XHCI_TRB_TYPE_TRANSFER 32u
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#define XHCI_TRB_TYPE_NORMAL 1u
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#define XHCI_TRB_TYPE_SETUP 2u
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#define XHCI_TRB_TYPE_DATA 3u
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#define XHCI_TRB_TYPE_STATUS 4u
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#define XHCI_TRB_TYPE_ENABLE_SLOT 9u
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#define XHCI_TRB_TYPE_ADDRESS_DEVICE 11u
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#define XHCI_TRB_TYPE_CONFIGURE_ENDPOINT 12u
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#define XHCI_CC_SUCCESS 1u
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#define XHCI_TRB_ISP (1u << 2)
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#define XHCI_TRB_IOC (1u << 5)
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#define XHCI_TRB_IDT (1u << 6)
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#define XHCI_TRB_DATA_DIR_IN (1u << 16)
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#define XHCI_TRB_SETUP_TRT_NONE (0u << 16)
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#define XHCI_TRB_SETUP_TRT_IN (3u << 16)
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#define XHCI_TRB_STATUS_DIR_IN (1u << 16)
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#define XHCI_HCC1_CSZ (1u << 2)
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#define XHCI_CONTEXT_ENTRIES(n) ((uint32_t)(n) << 27)
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#define XHCI_SLOT_SPEED(s) ((uint32_t)(s) << 20)
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#define XHCI_SLOT_ROOT_PORT(p) ((uint32_t)(p) << 16)
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#define XHCI_EP_TYPE_CONTROL (4u << 3)
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#define XHCI_EP_TYPE_BULK_OUT (2u << 3)
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#define XHCI_EP_TYPE_BULK_IN (6u << 3)
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#define XHCI_EP_TYPE_INT_IN (7u << 3)
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#define XHCI_EP_CERR_3 (3u << 1)
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#define XHCI_EP_DCS 1ull
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#define USB_REQ_GET_DESCRIPTOR 0x06u
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#define USB_REQ_SET_CONFIGURATION 0x09u
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#define USB_REQ_SET_IDLE 0x0Au
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#define USB_REQ_SET_PROTOCOL 0x0Bu
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#define USB_DESC_DEVICE 0x01u
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#define USB_DESC_CONFIGURATION 0x02u
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#define USB_DESC_INTERFACE 0x04u
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#define USB_DESC_ENDPOINT 0x05u
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#define USB_DESC_HID 0x21u
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#define USB_DESC_CS_INTERFACE 0x24u
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#define USB_DIR_OUT 0x00u
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#define USB_DIR_IN 0x80u
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#define USB_TYPE_STANDARD 0x00u
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#define USB_TYPE_CLASS 0x20u
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#define USB_RECIP_DEVICE 0x00u
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#define USB_RECIP_INTERFACE 0x01u
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#define USB_ENDPOINT_DIR_IN 0x80u
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#define USB_ENDPOINT_NUMBER_MASK 0x0Fu
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#define USB_ENDPOINT_ATTR_TYPE_MASK 0x03u
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#define USB_ENDPOINT_TYPE_CONTROL 0x00u
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#define USB_ENDPOINT_TYPE_ISOCH 0x01u
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#define USB_ENDPOINT_TYPE_BULK 0x02u
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#define USB_ENDPOINT_TYPE_INTERRUPT 0x03u
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#define USB_CLASS_HID 0x03u
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#define USB_CLASS_MASS_STORAGE 0x08u
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#define USB_MASS_SUBCLASS_SCSI 0x06u
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#define USB_MASS_PROTOCOL_BOT 0x50u
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#define USB_HID_SUBCLASS_BOOT 0x01u
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#define USB_HID_PROTOCOL_KEYBOARD 0x01u
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#define USB_HID_PROTOCOL_MOUSE 0x02u
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#define USB_MASS_BOT_CBW_SIGNATURE 0x43425355u
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#define USB_MASS_BOT_CSW_SIGNATURE 0x53425355u
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#define USB_MASS_BOT_CSW_PASSED 0u
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#define USB_MASS_BOT_CSW_FAILED 1u
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#define SCSI_TEST_UNIT_READY 0x00u
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#define SCSI_REQUEST_SENSE 0x03u
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#define SCSI_INQUIRY 0x12u
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#define SCSI_READ_10 0x28u
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#define SCSI_WRITE_10 0x2Au
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#define SCSI_READ_CAPACITY_10 0x25u
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#define XHCI_RING_TRBS 256u
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#define XHCI_EVENT_TRBS 256u
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#define XHCI_DCBAA_ENTRIES 256u
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#define XHCI_MMIO_FLOOR_BYTES 0x10000u
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#define XHCI_MAX_SCRATCHPADS 1024u
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#define XHCI_MAX_TRACKED_SLOTS 64u
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#define XHCI_MAX_ROOT_PORTS 255u
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#define XHCI_EP0_RING_TRBS 256u
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#define XHCI_HID_RING_TRBS 256u
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#define XHCI_BULK_RING_TRBS 256u
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#define XHCI_MAX_HID_REPORT 16u
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#define USB_STORAGE_DMA_PAGES 1u
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#define USB_STORAGE_MAX_BYTES (USB_STORAGE_DMA_PAGES * PAGE_SIZE)
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#define USB_STORAGE_SECTOR_SIZE 512u
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#define USB_MAX_TRACKED_INTERFACES 8u
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#define USB_MAX_TRACKED_ENDPOINTS 8u
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#pragma pack(push, 1)
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typedef struct XHCI_TRB {
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uint32_t ParameterLo;
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uint32_t ParameterHi;
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uint32_t Status;
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uint32_t Control;
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} XHCI_TRB;
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typedef struct XHCI_ERST_ENTRY {
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uint64_t RingSegmentBase;
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uint32_t RingSegmentSize;
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uint32_t Reserved;
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} XHCI_ERST_ENTRY;
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typedef struct USB_SETUP_PACKET {
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uint8_t bmRequestType;
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uint8_t bRequest;
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uint16_t wValue;
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uint16_t wIndex;
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uint16_t wLength;
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} USB_SETUP_PACKET;
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typedef struct USB_DEVICE_DESCRIPTOR {
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uint8_t bLength;
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uint8_t bDescriptorType;
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uint16_t bcdUSB;
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uint8_t bDeviceClass;
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uint8_t bDeviceSubClass;
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uint8_t bDeviceProtocol;
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uint8_t bMaxPacketSize0;
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uint16_t idVendor;
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uint16_t idProduct;
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uint16_t bcdDevice;
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uint8_t iManufacturer;
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uint8_t iProduct;
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uint8_t iSerialNumber;
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uint8_t bNumConfigurations;
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} USB_DEVICE_DESCRIPTOR;
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typedef struct USB_CONFIGURATION_DESCRIPTOR {
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uint8_t bLength;
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uint8_t bDescriptorType;
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uint16_t wTotalLength;
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uint8_t bNumInterfaces;
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uint8_t bConfigurationValue;
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uint8_t iConfiguration;
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uint8_t bmAttributes;
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uint8_t bMaxPower;
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} USB_CONFIGURATION_DESCRIPTOR;
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typedef struct USB_INTERFACE_DESCRIPTOR {
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uint8_t bLength;
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uint8_t bDescriptorType;
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uint8_t bInterfaceNumber;
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uint8_t bAlternateSetting;
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uint8_t bNumEndpoints;
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uint8_t bInterfaceClass;
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uint8_t bInterfaceSubClass;
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uint8_t bInterfaceProtocol;
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uint8_t iInterface;
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} USB_INTERFACE_DESCRIPTOR;
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typedef struct USB_ENDPOINT_DESCRIPTOR {
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uint8_t bLength;
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uint8_t bDescriptorType;
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uint8_t bEndpointAddress;
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uint8_t bmAttributes;
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uint16_t wMaxPacketSize;
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uint8_t bInterval;
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} USB_ENDPOINT_DESCRIPTOR;
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typedef struct USB_MASS_CBW {
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uint32_t Signature;
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uint32_t Tag;
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uint32_t DataTransferLength;
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uint8_t Flags;
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uint8_t Lun;
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uint8_t CommandBlockLength;
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uint8_t CommandBlock[16];
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} USB_MASS_CBW;
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typedef struct USB_MASS_CSW {
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uint32_t Signature;
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uint32_t Tag;
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uint32_t DataResidue;
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uint8_t Status;
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} USB_MASS_CSW;
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#pragma pack(pop)
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typedef struct USB_TRACKED_INTERFACE {
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bool Present;
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USB_INTERFACE_DESCRIPTOR Descriptor;
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uint8_t EndpointCount;
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USB_ENDPOINT_DESCRIPTOR Endpoints[USB_MAX_TRACKED_ENDPOINTS];
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} USB_TRACKED_INTERFACE;
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typedef enum USB_BAR_KIND {
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UsbBarNone,
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UsbBarIo,
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UsbBarMmio
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} USB_BAR_KIND;
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typedef struct USB_BAR {
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USB_BAR_KIND Kind;
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uint64_t Base;
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uint8_t Index;
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} USB_BAR;
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typedef struct XHCI_DEVICE {
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bool Allocated;
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bool Addressed;
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uint8_t SlotId;
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uint8_t Port;
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uint8_t Speed;
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uint16_t MaxPacketSize0;
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uint16_t VendorId;
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uint16_t ProductId;
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uint16_t BcdUsb;
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uint16_t BcdDevice;
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uint8_t DeviceClass;
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uint8_t DeviceSubclass;
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uint8_t DeviceProtocol;
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uint8_t ConfigurationValue;
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bool Configured;
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uint8_t InterfaceCount;
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USB_TRACKED_INTERFACE Interfaces[USB_MAX_TRACKED_INTERFACES];
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bool HidCandidate;
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bool HidActive;
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bool HidKeyboard;
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bool HidMouse;
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bool HidArmed;
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uint8_t HidInterface;
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uint8_t HidProtocol;
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uint8_t HidEndpointAddress;
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uint8_t HidEndpointId;
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uint8_t HidInterval;
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uint16_t HidMaxPacket;
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uint16_t HidReportLength;
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uint32_t HidEnqueue;
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uint8_t HidCycle;
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uint8_t HidLastModifiers;
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uint8_t HidLastKeys[6];
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uint8_t HidLastButtons;
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uint64_t HidLastTrbPhys;
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bool MassCandidate;
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bool MassActive;
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uint8_t MassInterface;
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uint8_t MassBulkInAddress;
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uint8_t MassBulkOutAddress;
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uint8_t MassBulkInEndpointId;
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uint8_t MassBulkOutEndpointId;
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uint16_t MassBulkInMaxPacket;
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uint16_t MassBulkOutMaxPacket;
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uint32_t MassInEnqueue;
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uint8_t MassInCycle;
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uint32_t MassOutEnqueue;
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uint8_t MassOutCycle;
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uint32_t MassTag;
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uint32_t MassBlockSize;
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uint64_t MassBlockCount;
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DEVICE_OBJECT* MassDeviceObject;
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volatile long MassIoBusy;
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PHYSICAL_ADDRESS InputContextPhys;
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PHYSICAL_ADDRESS DeviceContextPhys;
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PHYSICAL_ADDRESS Ep0RingPhys;
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PHYSICAL_ADDRESS HidRingPhys;
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PHYSICAL_ADDRESS MassInRingPhys;
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PHYSICAL_ADDRESS MassOutRingPhys;
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PHYSICAL_ADDRESS DescriptorPhys;
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PHYSICAL_ADDRESS HidBufferPhys;
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PHYSICAL_ADDRESS MassBufferPhys;
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uint8_t* InputContext;
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uint8_t* DeviceContext;
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XHCI_TRB* Ep0Ring;
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XHCI_TRB* HidRing;
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XHCI_TRB* MassInRing;
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XHCI_TRB* MassOutRing;
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uint8_t* DescriptorBuffer;
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uint8_t* HidBuffer;
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uint8_t* MassBuffer;
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uint32_t Ep0Enqueue;
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uint8_t Ep0Cycle;
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} XHCI_DEVICE;
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typedef struct XHCI_COMMAND_RESULT {
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uint32_t CompletionCode;
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uint8_t SlotId;
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} XHCI_COMMAND_RESULT;
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typedef struct XHCI_TRANSFER_RESULT {
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uint32_t CompletionCode;
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uint8_t SlotId;
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uint8_t EndpointId;
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uint32_t Residue;
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} XHCI_TRANSFER_RESULT;
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typedef struct XHCI_WAIT_TARGET {
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uint64_t CommandPhys;
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uint64_t TransferPhys;
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uint8_t TransferSlotId;
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uint8_t TransferEndpointId;
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bool CommandMatched;
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bool TransferMatched;
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XHCI_COMMAND_RESULT Command;
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XHCI_TRANSFER_RESULT Transfer;
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} XHCI_WAIT_TARGET;
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typedef struct XHCI_CONTROLLER {
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const HAL_API* Hal;
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uint8_t Bus;
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uint8_t Dev;
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uint8_t Fn;
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uint8_t Irq;
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bool UsingMsi;
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uint64_t MmioPhys;
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uint32_t MmioBytes;
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volatile uint8_t* Mmio;
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volatile uint8_t* Cap;
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volatile uint8_t* Op;
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volatile uint8_t* Runtime;
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volatile uint8_t* Doorbells;
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uint8_t CapLength;
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uint16_t Version;
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uint32_t Hcs1;
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uint32_t Hcs2;
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uint32_t Hcc1;
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uint32_t DbOff;
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uint32_t RtsOff;
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uint8_t MaxSlots;
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uint16_t MaxIntrs;
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uint8_t MaxPorts;
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uint16_t ScratchpadCount;
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uint8_t PortProtocolMajor[XHCI_MAX_ROOT_PORTS + 1u];
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uint8_t PortProtocolMinor[XHCI_MAX_ROOT_PORTS + 1u];
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PHYSICAL_ADDRESS DcbaaPhys;
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PHYSICAL_ADDRESS ScratchpadArrayPhys;
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PHYSICAL_ADDRESS ScratchpadPhys[XHCI_MAX_SCRATCHPADS];
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PHYSICAL_ADDRESS CommandRingPhys;
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PHYSICAL_ADDRESS EventRingPhys;
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PHYSICAL_ADDRESS ErstPhys;
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uint64_t* Dcbaa;
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uint64_t* ScratchpadArray;
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XHCI_TRB* CommandRing;
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XHCI_TRB* EventRing;
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XHCI_ERST_ENTRY* Erst;
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uint32_t CommandEnqueue;
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uint8_t CommandCycle;
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uint32_t EventDequeue;
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uint8_t EventCycle;
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uint8_t ContextBytes;
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XHCI_DEVICE Devices[XHCI_MAX_TRACKED_SLOTS + 1u];
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uint32_t HidDeviceCount;
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KDPC EventDpc;
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volatile bool InterruptsEnabled;
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volatile uint32_t InterruptCount;
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volatile uint32_t EventDpcCount;
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SPINLOCK EventLock;
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volatile XHCI_WAIT_TARGET* ActiveWait;
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volatile bool Running;
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} XHCI_CONTROLLER;
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extern XHCI_CONTROLLER gXhci;
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extern bool gHaveXhci;
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extern DRIVER_OBJECT gUsbStorageDriver;
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uint32_t UsbAlignUp32(uint32_t value, uint32_t align);
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void XhciBarrier(void);
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uint8_t XhciRead8(volatile uint8_t* base, uint32_t reg);
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uint16_t XhciRead16(volatile uint8_t* base, uint32_t reg);
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uint32_t XhciRead32(volatile uint8_t* base, uint32_t reg);
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void XhciWrite32(volatile uint8_t* base, uint32_t reg, uint32_t value);
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uint64_t XhciRead64(volatile uint8_t* base, uint32_t reg);
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void XhciWrite64(volatile uint8_t* base, uint32_t reg, uint64_t value);
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void UsbDelayUs(const HAL_API* hal, uint32_t us);
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bool UsbWaitSet32(const HAL_API* hal, volatile uint8_t* base, uint32_t reg, uint32_t mask, uint32_t timeoutUs);
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bool UsbWaitClear32(const HAL_API* hal, volatile uint8_t* base, uint32_t reg, uint32_t mask, uint32_t timeoutUs);
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bool UsbReadBar(const HAL_API* hal, uint8_t bus, uint8_t dev, uint8_t fn, uint8_t index, USB_BAR* out);
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KSTATUS UsbMapMmio(const HAL_API* hal, uint64_t physBase, uint32_t bytes, volatile uint8_t** outMmio);
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void* UsbDmaAllocPages(XHCI_CONTROLLER* xhci, size_t pages, PHYSICAL_ADDRESS* outPhys);
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uint16_t XhciScratchpadCount(uint32_t hcs2);
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uint32_t XhciTrbType(const XHCI_TRB* trb);
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uint32_t XhciCompletionCode(const XHCI_TRB* trb);
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uint8_t XhciEventSlotId(const XHCI_TRB* trb);
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uint8_t XhciEventEndpointId(const XHCI_TRB* trb);
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uint32_t XhciTransferResidue(const XHCI_TRB* trb);
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uint32_t* XhciInputControlContext(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
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uint32_t* XhciInputSlotContext(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
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uint32_t* XhciInputEndpointContext(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, uint8_t endpointId);
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uint32_t XhciEpMaxPacket(uint8_t speed);
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uint64_t UsbSetupPacketToU64(const USB_SETUP_PACKET* setup);
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const char* XhciPortSpeedName(uint32_t speed);
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void XhciParseSupportedProtocols(XHCI_CONTROLLER* xhci);
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uint8_t XhciPortProtocolMajor(XHCI_CONTROLLER* xhci, uint8_t port, uint32_t portsc);
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const char* UsbEndpointTypeName(uint8_t type);
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const char* UsbDirectionName(uint8_t endpointAddress);
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const char* UsbInterfaceClassName(uint8_t klass, uint8_t subclass, uint8_t proto);
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void XhciLogPortStatus(XHCI_CONTROLLER* xhci);
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void XhciAckInterrupter0(XHCI_CONTROLLER* xhci);
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void XhciUpdateErdp(XHCI_CONTROLLER* xhci);
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bool XhciDrainEventRing(XHCI_CONTROLLER* xhci, XHCI_WAIT_TARGET* target);
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bool XhciDrainEventRingLocked(XHCI_CONTROLLER* xhci, XHCI_WAIT_TARGET* target);
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bool XhciWaitTargetComplete(const XHCI_WAIT_TARGET* target);
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KSTATUS XhciWaitForTarget(XHCI_CONTROLLER* xhci, XHCI_WAIT_TARGET* target, uint32_t timeoutUs);
|
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void XhciEventDpcRoutine(KDPC* dpc, void* context, void* systemArgument1, void* systemArgument2);
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|
void XhciIsr(void);
|
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KSTATUS XhciBiosHandoff(XHCI_CONTROLLER* xhci);
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|
KSTATUS XhciStopAndReset(XHCI_CONTROLLER* xhci);
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|
KSTATUS XhciAllocateScratchpads(XHCI_CONTROLLER* xhci);
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|
KSTATUS XhciAllocateRuntimeMemory(XHCI_CONTROLLER* xhci);
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|
KSTATUS XhciProgramRuntime(XHCI_CONTROLLER* xhci);
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|
uint64_t XhciCommandTrbPhys(XHCI_CONTROLLER* xhci, uint32_t index);
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|
KSTATUS XhciSubmitCommand(XHCI_CONTROLLER* xhci, uint64_t parameter, uint32_t status, uint32_t controlWithoutCycle, XHCI_COMMAND_RESULT* outResult);
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|
KSTATUS XhciSubmitNoopCommand(XHCI_CONTROLLER* xhci);
|
|
KSTATUS XhciEnableSlot(XHCI_CONTROLLER* xhci, uint8_t* outSlotId);
|
|
KSTATUS XhciAddressDevice(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
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|
KSTATUS XhciStart(XHCI_CONTROLLER* xhci);
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|
void XhciEnableInterrupts(XHCI_CONTROLLER* xhci);
|
|
uint32_t XhciPortReg(uint8_t port);
|
|
void XhciClearPortChanges(XHCI_CONTROLLER* xhci, uint8_t port);
|
|
KSTATUS XhciResetPort(XHCI_CONTROLLER* xhci, uint8_t port, uint8_t* outSpeed);
|
|
KSTATUS XhciAllocateDeviceMemory(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
void XhciBuildDefaultControlContext(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
uint64_t XhciEp0TrbPhys(XHCI_DEVICE* dev, uint32_t index);
|
|
KSTATUS XhciEp0AppendTrb(XHCI_DEVICE* dev, uint64_t parameter, uint32_t status, uint32_t controlWithoutCycle, uint64_t* outPhys);
|
|
KSTATUS XhciControlIn(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, const USB_SETUP_PACKET* setup, void* buffer, PHYSICAL_ADDRESS bufferPhys, uint16_t length);
|
|
KSTATUS XhciControlNoData(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, const USB_SETUP_PACKET* setup);
|
|
KSTATUS XhciGetDeviceDescriptor(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, USB_DEVICE_DESCRIPTOR* outDesc);
|
|
KSTATUS XhciGetConfigurationDescriptor(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, uint8_t configurationIndex, USB_CONFIGURATION_DESCRIPTOR* outConfig, uint16_t* outTotalLength);
|
|
uint8_t XhciEndpointIdFromAddress(uint8_t endpointAddress);
|
|
uint8_t XhciInterruptInterval(uint8_t speed, uint8_t usbInterval);
|
|
KSTATUS XhciRingAppend(XHCI_TRB* ring, PHYSICAL_ADDRESS ringPhys, uint32_t trbCount, uint32_t* enqueue, uint8_t* cycle, uint64_t parameter, uint32_t status, uint32_t controlWithoutCycle, uint64_t* outPhys);
|
|
bool XhciHidKeyInReport(const uint8_t* keys, uint8_t key);
|
|
INPUT_KEY XhciHidModifierKey(uint8_t bit);
|
|
void XhciSubmitHidKey(INPUT_KEY key, bool pressed);
|
|
void XhciProcessBootKeyboardReport(XHCI_DEVICE* dev, const uint8_t* report, uint16_t len);
|
|
void XhciProcessBootMouseReport(XHCI_DEVICE* dev, const uint8_t* report, uint16_t len);
|
|
KSTATUS XhciArmHidInterruptIn(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
void XhciArmAllHid(XHCI_CONTROLLER* xhci);
|
|
void XhciHandleAsyncTransferEvent(XHCI_CONTROLLER* xhci, uint64_t trbPhys, uint32_t completionCode, uint8_t slotId, uint8_t endpointId, uint32_t residue);
|
|
KSTATUS XhciStartHidInterrupts(XHCI_CONTROLLER* xhci);
|
|
KSTATUS XhciSetHidBootProtocol(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS XhciAllocateHidMemory(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS XhciConfigureHidEndpoint(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
const IO_PUBLISHED_USB_ENDPOINT* UsbFindEndpoint(const IO_PUBLISHED_DEVICE* pub, uint8_t endpointType, bool wantIn);
|
|
bool UsbHidMatch(const IO_PUBLISHED_DEVICE* pub, void* context);
|
|
KSTATUS UsbHidBind(IO_PUBLISHED_DEVICE* pub, void* context);
|
|
void XhciInitialiseTransferRing(XHCI_TRB* ring, PHYSICAL_ADDRESS ringPhys, uint32_t trbCount, uint8_t cycle);
|
|
KSTATUS XhciBulkTransfer(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, uint8_t endpointId, XHCI_TRB* ring, PHYSICAL_ADDRESS ringPhys, uint32_t* enqueue, uint8_t* cycle, PHYSICAL_ADDRESS bufferPhys, uint32_t length, uint32_t* outActual);
|
|
KSTATUS UsbStorageBulkIn(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, PHYSICAL_ADDRESS phys, uint32_t length, uint32_t* outActual);
|
|
KSTATUS UsbStorageBulkOut(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, PHYSICAL_ADDRESS phys, uint32_t length, uint32_t* outActual);
|
|
KSTATUS UsbStorageBotCommand(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, const uint8_t* cdb, uint8_t cdbLen, void* data, PHYSICAL_ADDRESS dataPhys, uint32_t dataLength, bool dataIn);
|
|
uint32_t UsbBe32(const uint8_t* p);
|
|
void UsbStoreBe32(uint8_t* p, uint32_t v);
|
|
void UsbStoreBe16(uint8_t* p, uint16_t v);
|
|
KSTATUS UsbStorageInquiry(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS UsbStorageRequestSense(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS UsbStorageTestUnitReady(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS UsbStorageReadCapacity(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS UsbStorageReadWriteSectors(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, bool write, uint64_t lba, uint32_t sectors, void* buffer);
|
|
void UsbStorageAcquireIo(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
void UsbStorageReleaseIo(XHCI_DEVICE* dev);
|
|
KSTATUS UsbStorageDispatchReadWrite(DEVICE_OBJECT* device, IRP* irp);
|
|
KSTATUS XhciAllocateMassStorageMemory(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS XhciConfigureMassStorageEndpoints(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
uint8_t UsbFindFreeDiskIndex(void);
|
|
KSTATUS UsbStorageRegisterDisk(XHCI_DEVICE* dev);
|
|
bool UsbStorageMatch(const IO_PUBLISHED_DEVICE* pub, void* context);
|
|
KSTATUS UsbStorageBind(IO_PUBLISHED_DEVICE* pub, void* context);
|
|
KSTATUS UsbRegisterClassMatchers(void);
|
|
KSTATUS XhciSetConfiguration(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, uint8_t configurationValue);
|
|
void XhciLogConfigurationTree(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, const USB_CONFIGURATION_DESCRIPTOR* config, uint16_t totalLength);
|
|
void XhciPublishUsbInterfaces(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev);
|
|
KSTATUS XhciDiscoverAndSetConfiguration(XHCI_CONTROLLER* xhci, XHCI_DEVICE* dev, const USB_DEVICE_DESCRIPTOR* devDesc);
|
|
KSTATUS XhciEnumeratePort(XHCI_CONTROLLER* xhci, uint8_t port);
|
|
void XhciEnumerateRootPorts(XHCI_CONTROLLER* xhci);
|
|
KSTATUS XhciInitialise(const HAL_API* hal, uint8_t bus, uint8_t dev, uint8_t fn, uint16_t vendor, uint16_t device);
|