619 lines
19 KiB
C
619 lines
19 KiB
C
// HAL initialization entry point. This file discovers platform tables and publishes the HAL API to the kernel.
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#include <ntlite/ddi/hal_api.h>
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#include <kernel/hal/hal_apic.h>
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#include <kernel/hal/hal_output.h>
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#include <string.h>
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#include <stdint.h>
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#include <stdarg.h>
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#include <intrin.h>
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#include <common/printf.h>
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void HalScreenInitialize(void* (*AllocatePool)(size_t size), uintptr_t fb, int w, int h, int stride,
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HAL_SCREEN* out);
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KSTATUS HalTimerInitialize(uintptr_t lapicPhys, uintptr_t hpetPhys, HAL_TIMER *out);
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void HalPciInitialize(HAL_PCI* out);
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void HalRtcInitialize(HAL_RTC* out);
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void HalRtcSetCenturyRegister(uint8_t centuryRegister);
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extern void HalSetDebugEnabled(int v);
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// Defined in mm_virt.c - HAL needs it for MMIO window access.
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static uint64_t gPhysBase = 0xFFFF880000000000ULL;
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HAL_API gApi;
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static int gInitialised = 0;
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extern void (*gTimerCallback)(void);
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// ACPI table walker - minimal, just enough to find APIC and HPET addresses.
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#define ACPI_SIG(a,b,c,d) ((uint32_t)(a)|((uint32_t)(b)<<8)|((uint32_t)(c)<<16)|((uint32_t)(d)<<24))
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#pragma pack(push, 1)
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#pragma warning(disable : 4200)
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// ACPI RSDP (Root System Description Pointer).
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typedef struct {
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char Signature[8];
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uint8_t Checksum;
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char OEMID[6];
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uint8_t Revision;
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uint32_t RsdtAddress;
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uint32_t Length;
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uint64_t XsdtAddress;
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uint8_t ExtendedChecksum;
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uint8_t Padding[3];
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} RSDP;
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// ACPI SDT Header.
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typedef struct {
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char Signature[4];
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uint32_t Length;
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uint8_t Revision;
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uint8_t Checksum;
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char OEMID[6];
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char OEMTableID[8];
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uint32_t OEMRevision;
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uint32_t CreatorID;
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uint32_t CreatorRevision;
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} ACPISDTHeader;
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// RSDT (Root System Description Table).
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typedef struct {
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ACPISDTHeader Header;
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uint32_t PointerToOtherSDT[];
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} RSDT;
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// XSDT (Extended System Description Table).
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typedef struct {
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ACPISDTHeader Header;
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uint64_t PointerToOtherSDT[];
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} XSDT;
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// MADT (Multiple APIC Description Table).
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typedef struct {
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ACPISDTHeader Header;
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uint32_t LocalAPICAddress;
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uint32_t Flags;
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uint8_t Entries[];
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} MADT;
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#pragma pack(pop)
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static uintptr_t gLapicPhys = 0xFEE00000;
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static uintptr_t gIoapicPhys = 0xFEC00000;
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static uintptr_t gHpetPhys = 0xFED00000;
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static HAL_CPU_TOPOLOGY gCpuTopology;
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// ACPI power-off state (filled in by ParseFadt / ScanDsdtForS5).
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// Do not guess SLP_TYP on real hardware: these values are firmware-specific.
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static uint16_t gPm1aCntBlk = 0;
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static uint16_t gPm1bCntBlk = 0;
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static uint8_t gSlpTypA = 0;
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static uint8_t gSlpTypB = 0;
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static int gS5Found = 0;
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int debugEnabled = 0;
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int _fltused; // MSVC floating-point helper anchor.
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// Writes a formatted early HAL diagnostic through the output router.
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void HalDbgPrint(const char* fmt, ...) {
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if (!debugEnabled || !fmt || !gApi.Output.Write)
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return;
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char line[1024];
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va_list args;
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va_start(args, fmt);
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int count = vsnprintf_(line, sizeof(line), fmt, args);
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va_end(args);
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size_t length = 0;
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if (count > 0) {
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length = (size_t)count;
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if (length >= sizeof(line))
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length = sizeof(line) - 1u;
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}
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HAL_OUTPUT_RECORD record;
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record.Stream = HAL_OUTPUT_STREAM_DEBUG;
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record.Flags = 0;
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record.Foreground = 0x00CCCCCCu;
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record.Background = 0x00012456u;
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record.Buffer = line;
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record.Length = length;
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gApi.Output.Write(&record);
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}
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static void *HalPhysToVirt(uint64_t phys) {
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return (void *)(phys + gPhysBase);
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}
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// FADT (Fixed ACPI Description Table) offsets used here. ACPI 2.0+
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// systems may put the real DSDT and PM1 control registers in the extended
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// X_* fields, so do not rely only on the legacy 32-bit fields.
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#define FADT_DSDT_OFFSET 40u
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#define FADT_PM1A_CNT_BLK_OFFSET 64u
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#define FADT_PM1B_CNT_BLK_OFFSET 68u
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#define FADT_X_DSDT_OFFSET 140u
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#define FADT_X_PM1A_CNT_BLK_OFFSET 172u
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#define FADT_X_PM1B_CNT_BLK_OFFSET 184u
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#define FADT_CENTURY_OFFSET 108u
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#pragma pack(push, 1)
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typedef struct {
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uint8_t AddressSpaceId;
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uint8_t RegisterBitWidth;
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uint8_t RegisterBitOffset;
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uint8_t AccessSize;
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uint64_t Address;
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} ACPI_GAS;
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#pragma pack(pop)
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// Implements the acpi Read U32 operation.
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static uint32_t AcpiReadU32(const void* table, uint32_t tableLen, uint32_t off) {
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uint32_t value = 0;
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if (off + sizeof(value) <= tableLen)
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memcpy(&value, (const uint8_t*)table + off, sizeof(value));
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return value;
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}
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// Implements the acpi Read U64 operation.
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static uint64_t AcpiReadU64(const void* table, uint32_t tableLen, uint32_t off) {
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uint64_t value = 0;
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if (off + sizeof(value) <= tableLen)
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memcpy(&value, (const uint8_t*)table + off, sizeof(value));
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return value;
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}
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// Implements the acpi Read Gas Io Port operation.
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static uint16_t AcpiReadGasIoPort(const void* table, uint32_t tableLen, uint32_t off) {
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ACPI_GAS gas;
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if (off + sizeof(gas) > tableLen) return 0;
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memcpy(&gas, (const uint8_t*)table + off, sizeof(gas));
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// 0x01 == System I/O. HalShutdown currently writes PM1_CNT with outw(),
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// so ignore MMIO GAS entries until the HAL grows MMIO register access here.
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if (gas.AddressSpaceId != 0x01 || gas.Address == 0 || gas.Address > 0xFFFF)
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return 0;
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return (uint16_t)gas.Address;
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}
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static int AmlParsePkgLength(const uint8_t* p, const uint8_t* end,
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const uint8_t** body, const uint8_t** pkgEnd) {
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if (p >= end) return 0;
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const uint8_t* start = p;
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uint8_t first = *p++;
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uint32_t follow = first >> 6;
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uint32_t length;
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if (follow == 0) {
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length = first & 0x3F;
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} else {
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length = first & 0x0F;
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for (uint32_t i = 0; i < follow; i++) {
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if (p >= end) return 0;
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length |= ((uint32_t)*p++) << (4 + i * 8);
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}
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}
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if (start + length < p || start + length > end) return 0;
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*body = p;
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*pkgEnd = start + length;
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return 1;
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}
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static const uint8_t* AmlParseNameString(const uint8_t* p, const uint8_t* end,
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int* lastSegmentIsS5) {
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uint32_t segments = 1;
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*lastSegmentIsS5 = 0;
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// Optional root or parent prefixes: '\\', '^', '^^', ...
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while (p < end && (*p == 0x5C || *p == 0x5E)) p++;
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if (p >= end) return NULL;
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if (*p == 0x00) { // NullName
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return p + 1;
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} else if (*p == 0x2E) { // DualNamePrefix
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p++;
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segments = 2;
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} else if (*p == 0x2F) { // MultiNamePrefix
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p++;
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if (p >= end) return NULL;
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segments = *p++;
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}
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for (uint32_t s = 0; s < segments; s++) {
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if (p + 4 > end) return NULL;
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if (s == segments - 1 && memcmp(p, "_S5_", 4) == 0)
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*lastSegmentIsS5 = 1;
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p += 4;
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}
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return p;
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}
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// Implements the aml Read Integer operation.
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static int AmlReadInteger(const uint8_t** pp, const uint8_t* end, uint8_t* out) {
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const uint8_t* p = *pp;
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if (p >= end) return 0;
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switch (*p++) {
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case 0x00: // ZeroOp
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*out = 0;
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break;
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case 0x01: // OneOp
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*out = 1;
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break;
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case 0x0A: // BytePrefix
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if (p >= end) return 0;
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*out = *p++;
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break;
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case 0x0B: // WordPrefix
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if (p + 2 > end) return 0;
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*out = p[0];
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p += 2;
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break;
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case 0x0C: // DWordPrefix
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if (p + 4 > end) return 0;
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*out = p[0];
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p += 4;
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break;
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case 0x0E: // QWordPrefix
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if (p + 8 > end) return 0;
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*out = p[0];
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p += 8;
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break;
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default:
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return 0;
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}
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*pp = p;
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return 1;
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}
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// Scan DSDT AML for the _S5_ Name object and extract SLP_TYP values. Real
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// firmware commonly encodes the name as "\\_S5_" instead of just "_S5_", and
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// package integers may be ZeroOp/OneOp/Byte/Word/DWord/QWord constants.
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static void ScanDsdtForS5(const uint8_t* aml, uint32_t len) {
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const uint8_t* end = aml + len;
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for (const uint8_t* cur = aml; cur < end; cur++) {
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if (*cur != 0x08) continue; // NameOp
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const uint8_t* p = cur + 1;
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int isS5 = 0;
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p = AmlParseNameString(p, end, &isS5);
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if (!p || !isS5 || p >= end || *p != 0x12) continue; // PackageOp
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const uint8_t* body;
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const uint8_t* pkgEnd;
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if (!AmlParsePkgLength(p + 1, end, &body, &pkgEnd)) continue;
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if (body >= pkgEnd) continue;
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uint8_t elements = *body++;
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if (elements < 2) continue;
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uint8_t typA, typB;
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if (!AmlReadInteger(&body, pkgEnd, &typA)) continue;
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if (!AmlReadInteger(&body, pkgEnd, &typB)) continue;
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gSlpTypA = typA & 0x07;
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gSlpTypB = typB & 0x07;
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gS5Found = 1;
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HalDbgPrint("HAL: _S5_ SLP_TYP_A=0x%02x SLP_TYP_B=0x%02x\n",
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gSlpTypA, gSlpTypB);
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return;
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}
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HalDbgPrint("HAL: _S5_ not found in DSDT; ACPI shutdown disabled\n");
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}
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// Validates checksum.
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static int validate_checksum(void* table, uint32_t length) {
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uint8_t sum = 0;
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uint8_t* bytes = (uint8_t*)table;
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for (uint32_t i = 0; i < length; i++) {
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sum += bytes[i];
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}
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return sum == 0;
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}
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// Parses fadt.
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static void ParseFadt(const ACPISDTHeader* header) {
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const void* fadt = header;
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uint32_t len = header->Length;
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gPm1aCntBlk = (uint16_t)AcpiReadU32(fadt, len, FADT_PM1A_CNT_BLK_OFFSET);
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gPm1bCntBlk = (uint16_t)AcpiReadU32(fadt, len, FADT_PM1B_CNT_BLK_OFFSET);
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if (!gPm1aCntBlk)
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gPm1aCntBlk = AcpiReadGasIoPort(fadt, len, FADT_X_PM1A_CNT_BLK_OFFSET);
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if (!gPm1bCntBlk)
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gPm1bCntBlk = AcpiReadGasIoPort(fadt, len, FADT_X_PM1B_CNT_BLK_OFFSET);
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uint64_t dsdtPhys = AcpiReadU64(fadt, len, FADT_X_DSDT_OFFSET);
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if (!dsdtPhys)
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dsdtPhys = AcpiReadU32(fadt, len, FADT_DSDT_OFFSET);
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uint8_t centuryRegister = 0;
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if (FADT_CENTURY_OFFSET < len)
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centuryRegister = *((const uint8_t*)fadt + FADT_CENTURY_OFFSET);
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HalRtcSetCenturyRegister(centuryRegister);
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HalDbgPrint("HAL: FADT PM1a_CNT=0x%04x PM1b_CNT=0x%04x DSDT=0x%016llx RTC_CENTURY=0x%02x\n",
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gPm1aCntBlk, gPm1bCntBlk, dsdtPhys, centuryRegister);
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if (dsdtPhys) {
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const ACPISDTHeader* dsdt = (const ACPISDTHeader*)(dsdtPhys + gPhysBase);
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if (memcmp(dsdt->Signature, "DSDT", 4) == 0 &&
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// Validates checksum.
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validate_checksum((void*)dsdt, dsdt->Length)) {
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const uint8_t* aml = (const uint8_t*)(dsdt + 1);
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ScanDsdtForS5(aml, dsdt->Length - (uint32_t)sizeof(ACPISDTHeader));
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} else {
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HalDbgPrint("HAL: DSDT invalid or checksum failed\n");
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}
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}
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}
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// Implements the add Cpu Record operation.
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static void HalAddCpuRecord(uint32_t uid, uint32_t lapicId, uint32_t flags) {
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if (gCpuTopology.CpuCount >= HAL_MAX_CPUS)
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return;
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for (uint32_t i = 0; i < gCpuTopology.CpuCount; i++) {
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if (gCpuTopology.Cpus[i].LapicId == lapicId)
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return;
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}
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HAL_CPU_INFO* cpu = &gCpuTopology.Cpus[gCpuTopology.CpuCount++];
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memset(cpu, 0, sizeof(*cpu));
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cpu->ProcessorUid = uid;
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cpu->LapicId = lapicId;
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cpu->Flags = flags;
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cpu->Enabled = (flags & 1u) ? 1u : 0u;
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}
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// Parses madt.
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static void ParseMadt(MADT* madt) {
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gLapicPhys = madt->LocalAPICAddress;
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uint8_t* p = (uint8_t *)(madt + 1);
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uint8_t* end = (uint8_t *)madt + madt->Header.Length;
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while (p + 2 <= end) {
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uint8_t type = p[0], len = p[1];
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if (!len || p + len > end) break;
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if (type == 0 && len >= 8) { // Processor Local APIC
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uint32_t uid = p[2];
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uint32_t lapicId = p[3];
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uint32_t flags = *(uint32_t *)(p + 4);
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if (flags & 1u)
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HalAddCpuRecord(uid, lapicId, flags);
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} else if (type == 1 && len >= 12) { // I/O APIC entry
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gIoapicPhys = *(uint32_t *)(p + 4);
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} else if (type == 5 && len >= 12) { // Local APIC Address Override
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gLapicPhys = (uintptr_t)*(uint64_t *)(p + 4);
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} else if (type == 9 && len >= 16) { // Processor Local x2APIC
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uint32_t lapicId = *(uint32_t *)(p + 4);
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uint32_t flags = *(uint32_t *)(p + 8);
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uint32_t uid = *(uint32_t *)(p + 12);
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if (flags & 1u)
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HalAddCpuRecord(uid, lapicId, flags);
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}
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p += len;
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}
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}
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// Implements the walk Acpi operation.
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static void WalkAcpi(uintptr_t rsdpPhys) {
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if (!rsdpPhys) return;
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// Map RSDP into virtual memory.
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RSDP* rsdp = (RSDP*)(rsdpPhys + gPhysBase);
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if (memcmp(rsdp->Signature, "RSD PTR ", 8) != 0) {
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HalDbgPrint("HAL: Invalid RSDP signature!\n");
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return;
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}
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ACPISDTHeader* sdtHeader = NULL;
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uint32_t count = 0;
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int isXsdt = 0;
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// Safely find and validate the XSDT (ACPI 2.0+).
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if (rsdp->Revision >= 2 && rsdp->XsdtAddress != 0) {
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XSDT* xsdt = (XSDT*)(rsdp->XsdtAddress + gPhysBase);
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if (validate_checksum(xsdt, xsdt->Header.Length) &&
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// Implements the memcmp operation.
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memcmp(xsdt->Header.Signature, "XSDT", 4) == 0) {
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sdtHeader = &xsdt->Header;
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count = (xsdt->Header.Length - sizeof(ACPISDTHeader)) / 8;
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isXsdt = 1;
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}
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}
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// Fallback to safely finding and validating the RSDT (ACPI 1.0).
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if (sdtHeader == NULL && rsdp->RsdtAddress != 0) {
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RSDT* rsdt = (RSDT*)((uintptr_t)rsdp->RsdtAddress + gPhysBase);
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if (validate_checksum(rsdt, rsdt->Header.Length) &&
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// Implements the memcmp operation.
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memcmp(rsdt->Header.Signature, "RSDT", 4) == 0) {
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sdtHeader = &rsdt->Header;
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count = (rsdt->Header.Length - sizeof(ACPISDTHeader)) / 4;
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isXsdt = 0;
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}
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}
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if (sdtHeader == NULL) {
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HalDbgPrint("HAL: No valid XSDT or RSDT found!\n");
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return;
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}
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// Walk the tables.
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for (uint32_t i = 0; i < count; i++) {
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uintptr_t tablePhys = 0;
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if (isXsdt) {
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tablePhys = ((XSDT*)sdtHeader)->PointerToOtherSDT[i];
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} else {
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tablePhys = ((RSDT*)sdtHeader)->PointerToOtherSDT[i];
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}
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// Paranoid alignment check to reject firmware garbage pointers.
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if (!tablePhys || (tablePhys & 3) != 0) continue;
|
|
|
|
ACPISDTHeader* header = (ACPISDTHeader*)(tablePhys + gPhysBase);
|
|
|
|
// Ensure the table isn't corrupt before parsing.
|
|
if (!validate_checksum(header, header->Length)) continue;
|
|
|
|
// Parse MADT.
|
|
if (memcmp(header->Signature, "APIC", 4) == 0) {
|
|
ParseMadt((MADT*)header);
|
|
}
|
|
// Parse FADT (signature "FACP") for PM1 control ports and DSDT pointer.
|
|
else if (memcmp(header->Signature, "FACP", 4) == 0) {
|
|
ParseFadt(header);
|
|
}
|
|
// Parse HPET.
|
|
else if (memcmp(header->Signature, "HPET", 4) == 0) {
|
|
// HPET base address block is located at offset 44
|
|
// (which is 8 bytes past the 36-byte ACPISDTHeader).
|
|
gHpetPhys = *(uint64_t*)((uint8_t*)header + 44) & ~0xFFFULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
// HalShutdown - ACPI S5 soft power-off. Does not return.
|
|
static void HalShutdown(void) {
|
|
// Refuse further maskable interrupts before entering firmware power state.
|
|
(void)HalDisableInterrupts();
|
|
|
|
if (!gS5Found || !gPm1aCntBlk) {
|
|
// Refuse to guess. Guessing SLP_TYP is exactly how real hardware gets
|
|
// put into S3/S4 sleep instead of S5 soft-off.
|
|
HalStopProcessor();
|
|
}
|
|
|
|
// SLP_EN (bit 13) | SLP_TYPx (bits 12:10).
|
|
uint16_t valA = (uint16_t)(((uint16_t)gSlpTypA << 10) | (1 << 13));
|
|
uint16_t valB = (uint16_t)(((uint16_t)gSlpTypB << 10) | (1 << 13));
|
|
|
|
__outword(gPm1aCntBlk, valA);
|
|
if (gPm1bCntBlk) __outword(gPm1bCntBlk, valB);
|
|
|
|
HalStopProcessor();
|
|
}
|
|
|
|
__declspec(dllexport) KSTATUS HalGetProcessorTopology(HAL_CPU_TOPOLOGY* out) {
|
|
if (!out) return NTLSTATUS_INVALID_PARAMETER;
|
|
|
|
memset(out, 0, sizeof(*out));
|
|
*out = gCpuTopology;
|
|
|
|
if (!out->CpuCount) {
|
|
out->CpuCount = 1;
|
|
out->BspLapicId = HalGetBspLapicId();
|
|
out->Cpus[0].LapicId = out->BspLapicId;
|
|
out->Cpus[0].ProcessorUid = 0;
|
|
out->Cpus[0].Flags = 1;
|
|
out->Cpus[0].Enabled = 1;
|
|
out->Cpus[0].IsBsp = 1;
|
|
return NTLSTATUS_SUCCESS;
|
|
}
|
|
|
|
uint32_t bsp = HalGetBspLapicId();
|
|
out->BspLapicId = bsp;
|
|
int foundBsp = 0;
|
|
for (uint32_t i = 0; i < out->CpuCount; i++) {
|
|
out->Cpus[i].IsBsp = (out->Cpus[i].LapicId == bsp) ? 1u : 0u;
|
|
if (out->Cpus[i].IsBsp) foundBsp = 1;
|
|
}
|
|
|
|
if (!foundBsp && out->CpuCount < HAL_MAX_CPUS) {
|
|
HAL_CPU_INFO* cpu = &out->Cpus[out->CpuCount++];
|
|
memset(cpu, 0, sizeof(*cpu));
|
|
cpu->LapicId = bsp;
|
|
cpu->ProcessorUid = bsp;
|
|
cpu->Flags = 1;
|
|
cpu->Enabled = 1;
|
|
cpu->IsBsp = 1;
|
|
}
|
|
return NTLSTATUS_SUCCESS;
|
|
}
|
|
|
|
__declspec(dllexport) KSTATUS HalInitialize(const HAL_INIT_PARAMS* initParams) {
|
|
if (gInitialised) return NTLSTATUS_ALREADY_EXISTS;
|
|
gPhysBase = initParams->PhysicalWindowBase;
|
|
gApi.PhysToVirt = HalPhysToVirt;
|
|
debugEnabled = initParams->Debug;
|
|
|
|
HalOutputInitialize(&gApi.Output);
|
|
HalSerialInitialize(&gApi.Output);
|
|
|
|
// Screen follows serial so diagnostics still work without a framebuffer.
|
|
HalScreenInitialize(initParams->AllocatePool, initParams->FramebufferBase + initParams->PhysicalWindowBase,
|
|
(int)initParams->FramebufferWidth,
|
|
(int)initParams->FramebufferHeight,
|
|
(int)initParams->FramebufferStride,
|
|
&gApi.Screen);
|
|
HalScreenRegisterOutputEndpoint(&gApi.Output);
|
|
|
|
HalDbgPrint("HAL: screen %dx%d\n",
|
|
initParams->FramebufferWidth, initParams->FramebufferHeight);
|
|
|
|
// Parse ACPI to find LAPIC / IOAPIC / HPET addresses.
|
|
if (initParams->RsdpPhysical) WalkAcpi(initParams->RsdpPhysical);
|
|
HalDbgPrint("HAL: LAPIC=%016llx IOAPIC=%016llx HPET=%016llx\n",
|
|
gLapicPhys, gIoapicPhys, gHpetPhys);
|
|
|
|
HalApicInitialize(gLapicPhys, gIoapicPhys);
|
|
HalDbgPrint("HAL: local APIC mode=%s BSP_ID=%u\n",
|
|
HalApicUsingX2Apic() ? "x2APIC" : "xAPIC",
|
|
HalGetBspLapicId());
|
|
|
|
KSTATUS ts = HalTimerInitialize(gLapicPhys, gHpetPhys, &gApi.Timer);
|
|
if (!KSUCCESS(ts)) HalDbgPrint("HAL: HPET unavailable, using fallback\n");
|
|
|
|
HalRtcInitialize(&gApi.Rtc);
|
|
HalPciInitialize(&gApi.Pci);
|
|
gApi.Intc.RouteIrq = HalApicRouteIrq;
|
|
gApi.Intc.MaskIrq = HalApicMaskIrq;
|
|
gApi.Intc.UnmaskIrq = HalApicUnmaskIrq;
|
|
gApi.Intc.SendEoi = HalApicSendEoi;
|
|
|
|
gApi.Power.Shutdown = HalShutdown;
|
|
|
|
gApi.Version = HAL_API_VERSION;
|
|
gInitialised = 1;
|
|
|
|
// The 8042 can leave output bytes pending while the keyboard/mouse drivers
|
|
// are being brought up with interrupts temporarily disabled. Drain the
|
|
// controller before returning from HAL init so stale status/data bytes do
|
|
// not suppress the next keyboard or mouse interrupt edge.
|
|
for (int i = 0; i < 256; i++) {
|
|
if (__inbyte(0x64) & 0x01) {
|
|
__inbyte(0x60); // Consume
|
|
}
|
|
gApi.Timer.Stall(1); // Micro-stalls
|
|
}
|
|
|
|
HalDbgPrint("HAL: initialisation complete.\n");
|
|
return NTLSTATUS_SUCCESS;
|
|
}
|
|
|
|
// Registers scheduler.
|
|
__declspec(dllexport) void HalRegisterScheduler(void (*pKeSchedulerTick)(void)) {
|
|
gTimerCallback = pKeSchedulerTick;
|
|
}
|
|
|
|
// Returns api.
|
|
__declspec(dllexport) const HAL_API* HalGetApi(void) { return &gApi; }
|