612 lines
20 KiB
C
612 lines
20 KiB
C
// rtl816x.c - first-pass Realtek RTL8111/8168/8411 PCIe Gigabit NIC driver.
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//
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// Scope for this version:
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// * RTL8168/RTL8169-compatible PCI IDs, legacy INTx interrupt delivery.
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// * MMIO preferred, I/O BAR fallback.
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// * Descriptor-mode RX/TX with plain Ethernet frames.
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// * No checksum offload, TSO, VLAN, jumbo frames, MSI/MSI-X, or EEE.
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//
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// The driver registers a NET_DEVICE so a later ARP/IPv4/ICMP stack can attach
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// without knowing Realtek register details.
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <string.h>
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#include <intrin.h>
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#include <hal_api.h>
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#include <ke_status.h>
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#include <ke_debug.h>
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#include <ke_irq.h>
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#include <ke_dpc.h>
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#include <ke_spinlock.h>
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#include <mm_phys.h>
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#include <mm_virt.h>
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#include <net_device.h>
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#define RTL_VENDOR_REALTEK 0x10ECu
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#define RTL_DEVICE_8168 0x8168u
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#define RTL_DEVICE_8169 0x8169u
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#define PCI_REG_COMMAND 0x04u
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#define PCI_REG_BAR0 0x10u
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#define PCI_REG_IRQ 0x3Cu
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#define PCI_COMMAND_IO (1u << 0)
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#define PCI_COMMAND_MEMORY (1u << 1)
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#define PCI_COMMAND_MASTER (1u << 2)
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#define PCI_COMMAND_INTX_DISABLE (1u << 10)
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#define RTL_REG_MAC0 0x00u
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#define RTL_REG_MAR0 0x08u
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#define RTL_REG_TNPDS_LO 0x20u
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#define RTL_REG_TNPDS_HI 0x24u
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#define RTL_REG_THPDS_LO 0x28u
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#define RTL_REG_THPDS_HI 0x2Cu
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#define RTL_REG_CHIP_CMD 0x37u
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#define RTL_REG_TX_POLL 0x38u
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#define RTL_REG_INTR_MASK 0x3Cu
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#define RTL_REG_INTR_STAT 0x3Eu
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#define RTL_REG_TX_CONFIG 0x40u
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#define RTL_REG_RX_CONFIG 0x44u
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#define RTL_REG_CFG9346 0x50u
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#define RTL_REG_CONFIG1 0x52u
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#define RTL_REG_PHY_STATUS 0x6Cu
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#define RTL_REG_RX_MAXSIZE 0xDAu
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#define RTL_REG_CPLUS_CMD 0xE0u
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#define RTL_REG_RDSAR_LO 0xE4u
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#define RTL_REG_RDSAR_HI 0xE8u
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#define RTL_CMD_RESET 0x10u
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#define RTL_CMD_RX_ENABLE 0x08u
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#define RTL_CMD_TX_ENABLE 0x04u
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#define RTL_TXPOLL_NPQ 0x40u
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#define RTL_ISR_ROK 0x0001u
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#define RTL_ISR_RER 0x0002u
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#define RTL_ISR_TOK 0x0004u
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#define RTL_ISR_TER 0x0008u
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#define RTL_ISR_RXOVW 0x0010u
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#define RTL_ISR_LINKCHG 0x0020u
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#define RTL_ISR_FOVW 0x0040u
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#define RTL_ISR_TDU 0x0080u
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#define RTL_ISR_SWINT 0x0100u
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#define RTL_ISR_TIMEOUT 0x4000u
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#define RTL_ISR_SYSERR 0x8000u
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#define RTL_INTR_ENABLES (RTL_ISR_ROK | RTL_ISR_RER | RTL_ISR_TOK | RTL_ISR_TER | \
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RTL_ISR_RXOVW | RTL_ISR_LINKCHG | RTL_ISR_FOVW | \
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RTL_ISR_TDU | RTL_ISR_SYSERR)
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#define RTL_RXCFG_AAP (1u << 0) // accept all physical packets/promiscuous
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#define RTL_RXCFG_APM (1u << 1) // accept physical match
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#define RTL_RXCFG_AM (1u << 2) // accept multicast
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#define RTL_RXCFG_AB (1u << 3) // accept broadcast
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#define RTL_RXCFG_AR (1u << 4) // accept runt
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#define RTL_RXCFG_AER (1u << 5) // accept errored
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#define RTL_RXCFG_DMA_UNLIMITED (7u << 8)
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#define RTL_TXCFG_DMA_UNLIMITED (7u << 8)
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#define RTL_TXCFG_IFG (3u << 24)
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#define RTL_DESC_OWN (1u << 31)
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#define RTL_DESC_EOR (1u << 30)
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#define RTL_DESC_FS (1u << 29)
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#define RTL_DESC_LS (1u << 28)
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#define RTL_RXDESC_RES (1u << 21)
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#define RTL_RXDESC_RWT (1u << 22)
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#define RTL_RXDESC_CRC (1u << 19)
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#define RTL_RXDESC_RUNT (1u << 20)
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#define RTL_DESC_LENGTH_MASK 0x00003FFFu
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#define RTL_RX_COUNT 64u
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#define RTL_TX_COUNT 64u
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#define RTL_BUF_SIZE 2048u
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#define RTL_RX_WIRE_MAX (NET_ETHERNET_MAX_FRAME + 4u)
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#define RTL_RING_PAGES 1u
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#define RTL_RXBUF_PAGES ((RTL_RX_COUNT * RTL_BUF_SIZE + 4095u) / 4096u)
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#define RTL_TXBUF_PAGES ((RTL_TX_COUNT * RTL_BUF_SIZE + 4095u) / 4096u)
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#define RTL_MMIO_PAGES 1u
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#pragma pack(push, 1)
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typedef struct RTL_DESC {
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volatile uint32_t opts1;
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volatile uint32_t opts2;
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volatile uint32_t addrLo;
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volatile uint32_t addrHi;
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} RTL_DESC;
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#pragma pack(pop)
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typedef enum RTL_BAR_KIND {
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RtlBarNone = 0,
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RtlBarIo,
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RtlBarMmio,
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} RTL_BAR_KIND;
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typedef struct RTL_BAR {
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RTL_BAR_KIND Kind;
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uint64_t Base;
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uint8_t Index;
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} RTL_BAR;
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typedef struct RTL816X_DEVICE {
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uint8_t Bus;
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uint8_t Dev;
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uint8_t Fn;
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uint8_t Irq;
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uint16_t DeviceId;
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bool UseMmio;
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volatile uint8_t* Mmio;
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uint16_t IoBase;
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RTL_DESC* RxRing;
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RTL_DESC* TxRing;
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PHYSICAL_ADDRESS RxRingPhys;
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PHYSICAL_ADDRESS TxRingPhys;
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uint8_t* RxBuffers;
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uint8_t* TxBuffers;
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PHYSICAL_ADDRESS RxBuffersPhys;
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PHYSICAL_ADDRESS TxBuffersPhys;
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uint32_t RxIndex;
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uint32_t TxIndex;
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SPINLOCK TxLock;
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KDPC Dpc;
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volatile uint16_t PendingIsr;
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NET_DEVICE NetDevice;
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} RTL816X_DEVICE;
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static const HAL_API* gHal;
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static RTL816X_DEVICE gDevice;
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static bool gDevicePresent = false;
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static __forceinline void RtlMemoryBarrier(void) {
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_ReadWriteBarrier();
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_mm_mfence();
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_ReadWriteBarrier();
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}
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static uint8_t RtlRead8(RTL816X_DEVICE* r, uint32_t reg) {
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if (r->UseMmio)
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return *(volatile uint8_t*)(r->Mmio + reg);
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return __inbyte((unsigned short)(r->IoBase + reg));
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}
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static uint16_t RtlRead16(RTL816X_DEVICE* r, uint32_t reg) {
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if (r->UseMmio)
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return *(volatile uint16_t*)(r->Mmio + reg);
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return __inword((unsigned short)(r->IoBase + reg));
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}
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static uint32_t RtlRead32(RTL816X_DEVICE* r, uint32_t reg) {
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if (r->UseMmio)
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return *(volatile uint32_t*)(r->Mmio + reg);
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return __indword((unsigned short)(r->IoBase + reg));
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}
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static void RtlWrite8(RTL816X_DEVICE* r, uint32_t reg, uint8_t value) {
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if (r->UseMmio) *(volatile uint8_t*)(r->Mmio + reg) = value;
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else __outbyte((unsigned short)(r->IoBase + reg), value);
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}
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static void RtlWrite16(RTL816X_DEVICE* r, uint32_t reg, uint16_t value) {
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if (r->UseMmio) *(volatile uint16_t*)(r->Mmio + reg) = value;
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else __outword((unsigned short)(r->IoBase + reg), value);
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}
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static void RtlWrite32(RTL816X_DEVICE* r, uint32_t reg, uint32_t value) {
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if (r->UseMmio) *(volatile uint32_t*)(r->Mmio + reg) = value;
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else __outdword((unsigned short)(r->IoBase + reg), value);
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}
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static bool RtlFindDevice(uint8_t* outBus, uint8_t* outDev, uint8_t* outFn, uint16_t* outDeviceId) {
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if (gHal->Pci.FindDevice(RTL_VENDOR_REALTEK, RTL_DEVICE_8168, outBus, outDev, outFn)) {
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*outDeviceId = RTL_DEVICE_8168;
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return true;
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}
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if (gHal->Pci.FindDevice(RTL_VENDOR_REALTEK, RTL_DEVICE_8169, outBus, outDev, outFn)) {
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*outDeviceId = RTL_DEVICE_8169;
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return true;
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}
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return false;
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}
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static bool RtlReadBar(uint8_t bus, uint8_t dev, uint8_t fn, uint8_t index, RTL_BAR* out) {
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uint8_t reg = (uint8_t)(PCI_REG_BAR0 + index * 4u);
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uint32_t lo = gHal->Pci.Read32(bus, dev, fn, reg);
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out->Kind = RtlBarNone;
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out->Base = 0;
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out->Index = index;
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if (lo == 0 || lo == 0xFFFFFFFFu)
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return false;
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if (lo & 1u) {
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uint32_t base = lo & ~0x3u;
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if (!base) return false;
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out->Kind = RtlBarIo;
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out->Base = base;
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return true;
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}
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uint64_t base = (uint64_t)(lo & ~0xFu);
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uint32_t type = (lo >> 1) & 0x3u;
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if (type == 0x2u && index < 5) {
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uint32_t hi = gHal->Pci.Read32(bus, dev, fn, (uint8_t)(reg + 4u));
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base |= ((uint64_t)hi << 32);
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}
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if (!base) return false;
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out->Kind = RtlBarMmio;
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out->Base = base;
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return true;
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}
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static KSTATUS RtlMapMmio(uint64_t physBase, volatile uint8_t** outMmio) {
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uint64_t pageBase = physBase & PAGE_MASK;
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uint64_t pageOff = physBase - pageBase;
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for (uint32_t i = 0; i < RTL_MMIO_PAGES; i++) {
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PHYSICAL_ADDRESS phys = pageBase + (uint64_t)i * PAGE_SIZE;
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uintptr_t virt = (uintptr_t)gHal->PhysToVirt(phys);
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KSTATUS st = MmMapPage(virt, phys, PAGE_PRESENT | PAGE_WRITE | PAGE_NOCACHE);
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if (st == STATUS_ALREADY_EXISTS)
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st = MmSetPageProtect(virt, PAGE_SIZE, PAGE_PRESENT | PAGE_WRITE | PAGE_NOCACHE);
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if (!KSUCCESS(st))
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return st;
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}
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*outMmio = (volatile uint8_t*)((uintptr_t)gHal->PhysToVirt(pageBase) + pageOff);
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return STATUS_SUCCESS;
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}
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static KSTATUS RtlSelectRegisterBar(RTL816X_DEVICE* r) {
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RTL_BAR best = { RtlBarNone, 0, 0 };
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RTL_BAR fallback = { RtlBarNone, 0, 0 };
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for (uint8_t i = 0; i < 6; i++) {
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RTL_BAR bar;
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if (!RtlReadBar(r->Bus, r->Dev, r->Fn, i, &bar))
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continue;
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if (bar.Kind == RtlBarMmio) {
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best = bar;
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break;
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}
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if (bar.Kind == RtlBarIo && fallback.Kind == RtlBarNone)
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fallback = bar;
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// Skip the high dword of 64-bit memory BARs.
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if (bar.Kind == RtlBarMmio) {
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uint32_t lo = gHal->Pci.Read32(r->Bus, r->Dev, r->Fn, (uint8_t)(PCI_REG_BAR0 + i * 4u));
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if (((lo >> 1) & 0x3u) == 0x2u)
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i++;
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}
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}
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if (best.Kind == RtlBarNone)
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best = fallback;
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if (best.Kind == RtlBarMmio) {
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KSTATUS st = RtlMapMmio(best.Base, &r->Mmio);
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if (!KSUCCESS(st))
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return st;
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r->UseMmio = true;
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DbgPrint("RTL816X: BAR%u MMIO base=0x%llx virt=%p\n",
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best.Index, (unsigned long long)best.Base, r->Mmio);
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return STATUS_SUCCESS;
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}
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if (best.Kind == RtlBarIo) {
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if (best.Base > 0xFFFFu)
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return STATUS_NOT_SUPPORTED;
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r->IoBase = (uint16_t)best.Base;
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r->UseMmio = false;
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DbgPrint("RTL816X: BAR%u I/O base=0x%04x\n", best.Index, r->IoBase);
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return STATUS_SUCCESS;
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}
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return STATUS_NOT_FOUND;
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}
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static void RtlEnablePci(RTL816X_DEVICE* r) {
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uint32_t cmd = gHal->Pci.Read32(r->Bus, r->Dev, r->Fn, PCI_REG_COMMAND);
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cmd |= PCI_COMMAND_MASTER;
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if (r->UseMmio) cmd |= PCI_COMMAND_MEMORY;
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else cmd |= PCI_COMMAND_IO;
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cmd &= ~PCI_COMMAND_INTX_DISABLE;
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gHal->Pci.Write32(r->Bus, r->Dev, r->Fn, PCI_REG_COMMAND, cmd);
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}
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static KSTATUS RtlReset(RTL816X_DEVICE* r) {
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RtlWrite8(r, RTL_REG_CHIP_CMD, RTL_CMD_RESET);
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for (uint32_t i = 0; i < 1000; i++) {
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if ((RtlRead8(r, RTL_REG_CHIP_CMD) & RTL_CMD_RESET) == 0)
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return STATUS_SUCCESS;
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if (gHal->Timer.Stall)
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gHal->Timer.Stall(1000);
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}
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return STATUS_TIMEOUT;
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}
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static void RtlReadMac(RTL816X_DEVICE* r) {
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for (uint32_t i = 0; i < 6; i++)
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r->NetDevice.HardwareAddress[i] = RtlRead8(r, RTL_REG_MAC0 + i);
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r->NetDevice.HardwareAddressLength = 6;
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}
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static KSTATUS RtlAllocateDma(RTL816X_DEVICE* r) {
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r->RxRingPhys = MmAllocateContiguous(RTL_RING_PAGES);
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r->TxRingPhys = MmAllocateContiguous(RTL_RING_PAGES);
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r->RxBuffersPhys = MmAllocateContiguous(RTL_RXBUF_PAGES);
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r->TxBuffersPhys = MmAllocateContiguous(RTL_TXBUF_PAGES);
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if (!r->RxRingPhys || !r->TxRingPhys || !r->RxBuffersPhys || !r->TxBuffersPhys)
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return STATUS_NO_MEMORY;
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r->RxRing = (RTL_DESC*)gHal->PhysToVirt(r->RxRingPhys);
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r->TxRing = (RTL_DESC*)gHal->PhysToVirt(r->TxRingPhys);
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r->RxBuffers = (uint8_t*)gHal->PhysToVirt(r->RxBuffersPhys);
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r->TxBuffers = (uint8_t*)gHal->PhysToVirt(r->TxBuffersPhys);
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memset(r->RxRing, 0, PAGE_SIZE * RTL_RING_PAGES);
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memset(r->TxRing, 0, PAGE_SIZE * RTL_RING_PAGES);
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memset(r->RxBuffers, 0, PAGE_SIZE * RTL_RXBUF_PAGES);
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memset(r->TxBuffers, 0, PAGE_SIZE * RTL_TXBUF_PAGES);
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DbgPrint("RTL816X: rxRing=0x%llx txRing=0x%llx rxBuf=0x%llx txBuf=0x%llx\n",
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(unsigned long long)r->RxRingPhys,
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(unsigned long long)r->TxRingPhys,
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(unsigned long long)r->RxBuffersPhys,
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(unsigned long long)r->TxBuffersPhys);
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return STATUS_SUCCESS;
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}
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static void RtlInitDescriptors(RTL816X_DEVICE* r) {
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for (uint32_t i = 0; i < RTL_RX_COUNT; i++) {
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PHYSICAL_ADDRESS p = r->RxBuffersPhys + (PHYSICAL_ADDRESS)i * RTL_BUF_SIZE;
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r->RxRing[i].addrLo = (uint32_t)p;
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r->RxRing[i].addrHi = (uint32_t)(p >> 32);
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r->RxRing[i].opts2 = 0;
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r->RxRing[i].opts1 = RTL_DESC_OWN | RTL_BUF_SIZE | ((i == RTL_RX_COUNT - 1) ? RTL_DESC_EOR : 0);
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}
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for (uint32_t i = 0; i < RTL_TX_COUNT; i++) {
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PHYSICAL_ADDRESS p = r->TxBuffersPhys + (PHYSICAL_ADDRESS)i * RTL_BUF_SIZE;
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r->TxRing[i].addrLo = (uint32_t)p;
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r->TxRing[i].addrHi = (uint32_t)(p >> 32);
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r->TxRing[i].opts2 = 0;
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r->TxRing[i].opts1 = (i == RTL_TX_COUNT - 1) ? RTL_DESC_EOR : 0;
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}
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r->RxIndex = 0;
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r->TxIndex = 0;
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RtlMemoryBarrier();
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}
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static void RtlProgramHardware(RTL816X_DEVICE* r) {
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// Unlock the 9346-style config register window while programming.
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RtlWrite8(r, RTL_REG_CFG9346, 0xC0);
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// Disable interrupts while rings are being installed.
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RtlWrite16(r, RTL_REG_INTR_MASK, 0);
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RtlWrite16(r, RTL_REG_INTR_STAT, 0xFFFFu);
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// DMA ring base addresses.
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RtlWrite32(r, RTL_REG_TNPDS_LO, (uint32_t)r->TxRingPhys);
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RtlWrite32(r, RTL_REG_TNPDS_HI, (uint32_t)(r->TxRingPhys >> 32));
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RtlWrite32(r, RTL_REG_THPDS_LO, (uint32_t)r->TxRingPhys);
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RtlWrite32(r, RTL_REG_THPDS_HI, (uint32_t)(r->TxRingPhys >> 32));
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RtlWrite32(r, RTL_REG_RDSAR_LO, (uint32_t)r->RxRingPhys);
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RtlWrite32(r, RTL_REG_RDSAR_HI, (uint32_t)(r->RxRingPhys >> 32));
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// Plain packet mode. Keep C+ features mostly disabled for bring-up.
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RtlWrite16(r, RTL_REG_CPLUS_CMD, RtlRead16(r, RTL_REG_CPLUS_CMD) & ~(uint16_t)0x00E0u);
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RtlWrite16(r, RTL_REG_RX_MAXSIZE, RTL_BUF_SIZE);
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RtlWrite32(r, RTL_REG_TX_CONFIG, RTL_TXCFG_IFG | RTL_TXCFG_DMA_UNLIMITED);
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RtlWrite32(r, RTL_REG_RX_CONFIG,
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RTL_RXCFG_APM | RTL_RXCFG_AB | RTL_RXCFG_AM | RTL_RXCFG_DMA_UNLIMITED);
|
|
|
|
RtlMemoryBarrier();
|
|
|
|
// Enable receiver and transmitter.
|
|
RtlWrite8(r, RTL_REG_CHIP_CMD, RTL_CMD_RX_ENABLE | RTL_CMD_TX_ENABLE);
|
|
|
|
// Lock config space again and enable selected interrupts.
|
|
RtlWrite8(r, RTL_REG_CFG9346, 0x00);
|
|
RtlWrite16(r, RTL_REG_INTR_STAT, 0xFFFFu);
|
|
RtlWrite16(r, RTL_REG_INTR_MASK, RTL_INTR_ENABLES);
|
|
}
|
|
|
|
static void RtlHandleRx(RTL816X_DEVICE* r) {
|
|
for (uint32_t budget = 0; budget < RTL_RX_COUNT; budget++) {
|
|
RTL_DESC* d = &r->RxRing[r->RxIndex];
|
|
uint32_t opts = d->opts1;
|
|
if (opts & RTL_DESC_OWN)
|
|
break;
|
|
|
|
uint32_t keepEor = opts & RTL_DESC_EOR;
|
|
uint32_t len = opts & RTL_DESC_LENGTH_MASK;
|
|
bool good = ((opts & (RTL_RXDESC_RES | RTL_RXDESC_RWT | RTL_RXDESC_CRC | RTL_RXDESC_RUNT)) == 0) &&
|
|
((opts & (RTL_DESC_FS | RTL_DESC_LS)) == (RTL_DESC_FS | RTL_DESC_LS)) &&
|
|
len >= NET_ETHERNET_HEADER_LENGTH && len <= RTL_RX_WIRE_MAX;
|
|
|
|
if (good) {
|
|
// Realtek reports the Ethernet FCS in the descriptor length on many
|
|
// chips. Remove it when present so upper layers see a normal frame.
|
|
if (len > 4)
|
|
len -= 4;
|
|
if (len > NET_ETHERNET_MAX_FRAME) {
|
|
DbgPrint("RTL816X: dropping oversize frame len=%u\n", len);
|
|
} else {
|
|
NetReceiveFrame(&r->NetDevice,
|
|
r->RxBuffers + r->RxIndex * RTL_BUF_SIZE,
|
|
len);
|
|
}
|
|
} else {
|
|
DbgPrint("RTL816X: rx descriptor %u error opts=0x%08x len=%u\n",
|
|
r->RxIndex, opts, len);
|
|
}
|
|
|
|
d->opts2 = 0;
|
|
RtlMemoryBarrier();
|
|
d->opts1 = RTL_DESC_OWN | RTL_BUF_SIZE | keepEor;
|
|
RtlMemoryBarrier();
|
|
|
|
r->RxIndex = (r->RxIndex + 1) % RTL_RX_COUNT;
|
|
}
|
|
}
|
|
|
|
static void RtlDpcRoutine(KDPC* dpc, void* context, void* systemArgument1, void* systemArgument2) {
|
|
(void)dpc;
|
|
(void)systemArgument1;
|
|
(void)systemArgument2;
|
|
|
|
RTL816X_DEVICE* r = (RTL816X_DEVICE*)context;
|
|
uint16_t status = (uint16_t)r->PendingIsr;
|
|
r->PendingIsr = 0;
|
|
|
|
if (status & (RTL_ISR_ROK | RTL_ISR_RER | RTL_ISR_RXOVW | RTL_ISR_FOVW))
|
|
RtlHandleRx(r);
|
|
|
|
if (status & RTL_ISR_LINKCHG) {
|
|
uint8_t phy = RtlRead8(r, RTL_REG_PHY_STATUS);
|
|
DbgPrint("RTL816X: link change phy=0x%02x\n", phy);
|
|
}
|
|
|
|
if (status & (RTL_ISR_TER | RTL_ISR_SYSERR))
|
|
DbgPrint("RTL816X: interrupt status error bits=0x%04x\n", status);
|
|
}
|
|
|
|
static void RtlIsr(void) {
|
|
if (!gDevicePresent)
|
|
return;
|
|
|
|
RTL816X_DEVICE* r = &gDevice;
|
|
uint16_t status = RtlRead16(r, RTL_REG_INTR_STAT);
|
|
if (!status || status == 0xFFFFu)
|
|
return;
|
|
|
|
RtlWrite16(r, RTL_REG_INTR_STAT, status);
|
|
r->PendingIsr |= status;
|
|
KeInsertQueueDpc(&r->Dpc, (void*)0, (void*)0);
|
|
}
|
|
|
|
static KSTATUS RtlSendFrame(NET_DEVICE* device, const void* frame, size_t length) {
|
|
if (!device || !frame)
|
|
return STATUS_INVALID_PARAMETER;
|
|
if (length > NET_ETHERNET_MAX_FRAME)
|
|
return STATUS_BUFFER_TOO_SMALL;
|
|
if (length < NET_ETHERNET_HEADER_LENGTH)
|
|
return STATUS_INVALID_PARAMETER;
|
|
|
|
RTL816X_DEVICE* r = (RTL816X_DEVICE*)device->DriverContext;
|
|
if (!r)
|
|
return STATUS_INVALID_PARAMETER;
|
|
|
|
uintptr_t flags = KeAcquireSpinlock(&r->TxLock);
|
|
uint32_t index = r->TxIndex;
|
|
RTL_DESC* d = &r->TxRing[index];
|
|
uint32_t opts = d->opts1;
|
|
if (opts & RTL_DESC_OWN) {
|
|
KeReleaseSpinlock(&r->TxLock, flags);
|
|
return STATUS_QUEUE_FULL;
|
|
}
|
|
|
|
size_t wireLength = length < NET_ETHERNET_MIN_FRAME ? NET_ETHERNET_MIN_FRAME : length;
|
|
uint8_t* buf = r->TxBuffers + index * RTL_BUF_SIZE;
|
|
memcpy(buf, frame, length);
|
|
if (wireLength > length)
|
|
memset(buf + length, 0, wireLength - length);
|
|
|
|
uint32_t eor = opts & RTL_DESC_EOR;
|
|
d->opts2 = 0;
|
|
RtlMemoryBarrier();
|
|
d->opts1 = RTL_DESC_OWN | RTL_DESC_FS | RTL_DESC_LS | eor | (uint32_t)wireLength;
|
|
RtlMemoryBarrier();
|
|
RtlWrite8(r, RTL_REG_TX_POLL, RTL_TXPOLL_NPQ);
|
|
|
|
r->TxIndex = (index + 1) % RTL_TX_COUNT;
|
|
KeReleaseSpinlock(&r->TxLock, flags);
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
static KSTATUS RtlInitialize(const HAL_API* hal) {
|
|
gHal = hal;
|
|
memset(&gDevice, 0, sizeof(gDevice));
|
|
gDevice.TxLock = (SPINLOCK)SPINLOCK_INIT;
|
|
|
|
uint16_t deviceId;
|
|
if (!RtlFindDevice(&gDevice.Bus, &gDevice.Dev, &gDevice.Fn, &deviceId)) {
|
|
DbgPrint("RTL816X: no RTL8168/RTL8169 PCI device found; skipping\n");
|
|
return STATUS_SUCCESS;
|
|
}
|
|
gDevice.DeviceId = deviceId;
|
|
|
|
DbgPrint("RTL816X: found Realtek PCI device 10ec:%04x at %u:%u.%u\n",
|
|
deviceId, gDevice.Bus, gDevice.Dev, gDevice.Fn);
|
|
|
|
KSTATUS st = RtlSelectRegisterBar(&gDevice);
|
|
if (!KSUCCESS(st)) {
|
|
DbgPrint("RTL816X: no usable register BAR (0x%x)\n", st);
|
|
return st;
|
|
}
|
|
|
|
RtlEnablePci(&gDevice);
|
|
|
|
gDevice.Irq = hal->Pci.GetIrqLine(gDevice.Bus, gDevice.Dev, gDevice.Fn);
|
|
if (gDevice.Irq == 0xFFu) {
|
|
DbgPrint("RTL816X: no legacy PCI IRQ line wired\n");
|
|
return STATUS_NOT_SUPPORTED;
|
|
}
|
|
|
|
st = RtlReset(&gDevice);
|
|
if (!KSUCCESS(st)) {
|
|
DbgPrint("RTL816X: reset timed out\n");
|
|
return st;
|
|
}
|
|
|
|
RtlReadMac(&gDevice);
|
|
DbgPrint("RTL816X: MAC %02x:%02x:%02x:%02x:%02x:%02x irq=%u\n",
|
|
gDevice.NetDevice.HardwareAddress[0], gDevice.NetDevice.HardwareAddress[1],
|
|
gDevice.NetDevice.HardwareAddress[2], gDevice.NetDevice.HardwareAddress[3],
|
|
gDevice.NetDevice.HardwareAddress[4], gDevice.NetDevice.HardwareAddress[5],
|
|
gDevice.Irq);
|
|
|
|
st = RtlAllocateDma(&gDevice);
|
|
if (!KSUCCESS(st))
|
|
return st;
|
|
|
|
RtlInitDescriptors(&gDevice);
|
|
KeInitializeDpc(&gDevice.Dpc, RtlDpcRoutine, &gDevice);
|
|
|
|
gDevice.NetDevice.Mtu = NET_MTU_ETHERNET;
|
|
gDevice.NetDevice.DriverContext = &gDevice;
|
|
gDevice.NetDevice.SendFrame = RtlSendFrame;
|
|
RtlProgramHardware(&gDevice);
|
|
|
|
gDevicePresent = true;
|
|
KeIrqRegister(gDevice.Irq, RtlIsr);
|
|
|
|
st = NetRegisterDevice(&gDevice.NetDevice);
|
|
if (!KSUCCESS(st))
|
|
return st;
|
|
|
|
DbgPrint("RTL816X: initialized; RX/TX enabled on IRQ %u\n", gDevice.Irq);
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
KSTATUS DriverEntry(const HAL_API* hal) {
|
|
DbgPrint("RTL816X: driver loading...\n");
|
|
KSTATUS st = RtlInitialize(hal);
|
|
if (!KSUCCESS(st))
|
|
DbgPrint("RTL816X: init failed: 0x%x\n", st);
|
|
return st;
|
|
}
|