// ATA compatibility driver definitions shared by the storage implementation.

#pragma once

#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include <string.h>
#include <intrin.h>

#include <ntlite/ddk/ddk.h>
#include <ntlite/ddi/io_driver.h>
#include <ntlite/ddi/pci.h>
#include <ntlite/status.h>
#include <ntlite/ddk/debug.h>
#include <ntlite/ddk/irp.h>
#include <ntlite/ddk/scheduler.h>
#include <ntlite/ddk/semaphore.h>
#include <ntlite/ddk/thread.h>
#include <ntlite/ddk/event.h>
#include <ntlite/ddk/memory.h>

#define ATA_CONTROLLER_MAGIC 0x41544143u // ATAC
#define ATA_DEVICE_MAGIC     0x41544144u // ATAD

#define ATA_MAX_CONTROLLERS          8u
#define ATA_CHANNEL_COUNT            2u
#define ATA_DRIVES_PER_CHANNEL       2u
#define ATA_MAX_DEVICES_PER_CTL      (ATA_CHANNEL_COUNT * ATA_DRIVES_PER_CHANNEL)

#define ATA_PRIMARY_LEGACY_CMD_BASE  0x1F0u
#define ATA_PRIMARY_LEGACY_CTL_BASE  0x3F6u
#define ATA_PRIMARY_LEGACY_IRQ       14u
#define ATA_SECONDARY_LEGACY_CMD_BASE 0x170u
#define ATA_SECONDARY_LEGACY_CTL_BASE 0x376u
#define ATA_SECONDARY_LEGACY_IRQ     15u

#define ATA_REG_DATA                 0x00u
#define ATA_REG_ERROR                0x01u
#define ATA_REG_FEATURES             0x01u
#define ATA_REG_SECTOR_COUNT         0x02u
#define ATA_REG_LBA0                 0x03u
#define ATA_REG_LBA1                 0x04u
#define ATA_REG_LBA2                 0x05u
#define ATA_REG_DRIVE_HEAD           0x06u
#define ATA_REG_STATUS               0x07u
#define ATA_REG_COMMAND              0x07u
#define ATA_REG_ALT_STATUS           0x00u
#define ATA_REG_DEVICE_CONTROL       0x00u

#define ATA_DEVICE_CONTROL_NIEN       0x02u
#define ATA_DEVICE_CONTROL_SRST       0x04u

#define ATA_STATUS_ERR               0x01u
#define ATA_STATUS_DRQ               0x08u
#define ATA_STATUS_DF                0x20u
#define ATA_STATUS_DRDY              0x40u
#define ATA_STATUS_BSY               0x80u

#define ATA_CMD_READ_SECTORS         0x20u
#define ATA_CMD_WRITE_SECTORS        0x30u
#define ATA_CMD_CACHE_FLUSH          0xE7u
#define ATA_CMD_IDENTIFY_DEVICE      0xECu
#define ATA_CMD_READ_SECTORS_EXT     0x24u
#define ATA_CMD_WRITE_SECTORS_EXT    0x34u
#define ATA_CMD_CACHE_FLUSH_EXT      0xEAu

#define ATA_IDENT_CAPABILITIES       49u
#define ATA_IDENT_COMMAND_SETS       83u
#define ATA_IDENT_LBA28_SECTORS_LO   60u
#define ATA_IDENT_LBA28_SECTORS_HI   61u
#define ATA_IDENT_LBA48_SECTORS      100u
#define ATA_IDENT_LBA_SUPPORTED      (1u << 9)
#define ATA_IDENT_LBA48_SUPPORTED    (1u << 10)

#define ATA_SECTOR_SIZE              512u
#define ATA_POLL_TIMEOUT_US          250000u
#define ATA_RESET_TIMEOUT_US         5000000u
#define ATA_POLL_INTERVAL_US         10u
#define ATA_RESET_ASSERT_US          5u
#define ATA_RESET_SETTLE_US          2000u

struct ATA_CONTROLLER;
struct ATA_CHANNEL;

typedef struct ATA_DEVICE {
    uint32_t Magic;
    struct ATA_CONTROLLER* Controller;
    struct ATA_CHANNEL* Channel;

    DEVICE_OBJECT* DeviceObject;
    uint8_t Drive; // 0=master, 1=slave
    uint8_t DiskIndex;

    bool Present;
    bool SupportsLba48;
    uint64_t SectorCount;

    IRP_QUEUE IrpQueue;
    SEMAPHORE* IrpSemaphore;
    IO_REMOVE_LOCK RemoveLock;
    THREAD* WorkerThread;
    EVENT* WorkerFinished;
    volatile bool WorkerRunning;
} ATA_DEVICE;

typedef struct ATA_CHANNEL {
    struct ATA_CONTROLLER* Controller;
    uint8_t Index;

    uint16_t CommandBase;
    uint16_t ControlBase;
    uint8_t Irq;
    bool NativeMode;

    SEMAPHORE* Lock;
    ATA_DEVICE Devices[ATA_DRIVES_PER_CHANNEL];
} ATA_CHANNEL;

typedef struct ATA_CONTROLLER {
    uint32_t Magic;

    DEVICE_OBJECT* Fdo;
    DEVICE_OBJECT* Pdo;
    DEVICE_OBJECT* LowerDevice;

    PCI_DEVICE_INFO PciInfo;
    bool Started;
    bool Removed;
    bool SurpriseRemoved;

    ATA_CHANNEL Channels[ATA_CHANNEL_COUNT];
    uint8_t DeviceCount;
} ATA_CONTROLLER;

KSTATUS AtaAddDevice(DRIVER_OBJECT* driver, DEVICE_OBJECT* physicalDeviceObject);
KSTATUS AtaDispatchPnp(DEVICE_OBJECT* device, IRP* irp);
KSTATUS AtaDispatchReadWrite(DEVICE_OBJECT* device, IRP* irp);