// rtl8139.h - shared rtl8139 driver internals.
#pragma once

#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <string.h>
#include <intrin.h>

#include <ntlite/ddi/hal_api.h>
#include <ntlite/status.h>
#include <kernel/ke_debug.h>
#include <kernel/ke_irq.h>
#include <kernel/ke_dpc.h>
#include <kernel/ke_spinlock.h>
#include <kernel/mm_phys.h>
#include <kernel/mm_virt.h>
#include <ntlite/ddi/net_device.h>

#define RTL8139_VENDOR_REALTEK 0x10ECu
#define RTL8139_DEVICE_ID      0x8139u

#define PCI_REG_COMMAND        0x04u
#define PCI_REG_BAR0           0x10u
#define PCI_COMMAND_IO         (1u << 0)
#define PCI_COMMAND_MEMORY     (1u << 1)
#define PCI_COMMAND_MASTER     (1u << 2)
#define PCI_COMMAND_INTX_DISABLE (1u << 10)

#define RTL8139_REG_IDR0       0x00u
#define RTL8139_REG_MAR0       0x08u
#define RTL8139_REG_TSD0       0x10u
#define RTL8139_REG_TSAD0      0x20u
#define RTL8139_REG_RBSTART    0x30u
#define RTL8139_REG_CMD        0x37u
#define RTL8139_REG_CAPR       0x38u
#define RTL8139_REG_CBR        0x3Au
#define RTL8139_REG_IMR        0x3Cu
#define RTL8139_REG_ISR        0x3Eu
#define RTL8139_REG_TCR        0x40u
#define RTL8139_REG_RCR        0x44u
#define RTL8139_REG_CONFIG1    0x52u

#define RTL8139_CMD_BUFE       0x01u
#define RTL8139_CMD_TE         0x04u
#define RTL8139_CMD_RE         0x08u
#define RTL8139_CMD_RST        0x10u

#define RTL8139_ISR_ROK        0x0001u
#define RTL8139_ISR_RER        0x0002u
#define RTL8139_ISR_TOK        0x0004u
#define RTL8139_ISR_TER        0x0008u
#define RTL8139_ISR_RXOVW      0x0010u
#define RTL8139_ISR_PUN        0x0020u
#define RTL8139_ISR_FOVW       0x0040u
#define RTL8139_ISR_LENCHG     0x2000u
#define RTL8139_ISR_TIMEOUT    0x4000u
#define RTL8139_ISR_SYSERR     0x8000u

#define RTL8139_INTR_ENABLES   (RTL8139_ISR_ROK | RTL8139_ISR_RER | RTL8139_ISR_TOK | \
                                RTL8139_ISR_TER | RTL8139_ISR_RXOVW | RTL8139_ISR_PUN | \
                                RTL8139_ISR_FOVW | RTL8139_ISR_LENCHG | RTL8139_ISR_SYSERR)

#define RTL8139_RCR_AAP        (1u << 0)
#define RTL8139_RCR_APM        (1u << 1)
#define RTL8139_RCR_AM         (1u << 2)
#define RTL8139_RCR_AB         (1u << 3)
#define RTL8139_RCR_AR         (1u << 4)
#define RTL8139_RCR_AER        (1u << 5)
#define RTL8139_RCR_WRAP       (1u << 7)
#define RTL8139_RCR_MXDMA_UNLIMITED (7u << 8)
#define RTL8139_RCR_RBLEN_8K   (0u << 11)

#define RTL8139_TCR_MXDMA_UNLIMITED (7u << 8)
#define RTL8139_TCR_IFG_NORMAL      (3u << 24)

#define RTL8139_TSD_SIZE_MASK  0x00001FFFu
#define RTL8139_TSD_OWN        (1u << 13)
#define RTL8139_TSD_TUN        (1u << 14)
#define RTL8139_TSD_TOK        (1u << 15)
#define RTL8139_TSD_TABT       (1u << 30)

#define RTL8139_RX_OK          0x0001u
#define RTL8139_RX_BAD_BITS    0x003Eu // FAE | CRC | LONG | RUNT | ISE; MAR/PAM/BAR are valid match flags.

#define RTL8139_TX_SLOTS       4u
#define RTL8139_TX_BUF_SIZE    2048u
#define RTL8139_RX_RING_SIZE   8192u
#define RTL8139_RX_PAD         16u
#define RTL8139_RX_GUARD       1500u
#define RTL8139_RX_ALLOC_SIZE  (RTL8139_RX_RING_SIZE + RTL8139_RX_PAD + RTL8139_RX_GUARD)
#define RTL8139_RX_PAGES       ((RTL8139_RX_ALLOC_SIZE + 4095u) / 4096u)
#define RTL8139_TX_PAGES       (((RTL8139_TX_SLOTS * RTL8139_TX_BUF_SIZE) + 4095u) / 4096u)
#define RTL8139_MMIO_PAGES     1u
#define RTL8139_RX_WIRE_MAX   (NET_ETHERNET_MAX_FRAME + 4u)

#define RTL8139_REG_TSD(slot)  (RTL8139_REG_TSD0 + ((slot) * 4u))
#define RTL8139_REG_TSAD(slot) (RTL8139_REG_TSAD0 + ((slot) * 4u))

typedef enum RTL8139_BAR_KIND {
    Rtl8139BarNone = 0,
    Rtl8139BarIo,
    Rtl8139BarMmio,
} RTL8139_BAR_KIND;

typedef struct RTL8139_BAR {
    RTL8139_BAR_KIND Kind;
    uint64_t         Base;
    uint8_t          Index;
} RTL8139_BAR;

typedef struct RTL8139_DEVICE {
    uint8_t Bus;
    uint8_t Dev;
    uint8_t Fn;
    uint8_t Irq;

    bool UseMmio;
    volatile uint8_t* Mmio;
    uint16_t IoBase;

    PHYSICAL_ADDRESS RxPhys;
    PHYSICAL_ADDRESS TxPhys;
    uint8_t* RxBuffer;
    uint8_t* TxBuffers;
    uint8_t  RxScratch[RTL8139_TX_BUF_SIZE];

    uint32_t RxOffset;
    uint32_t TxSlot;
    SPINLOCK TxLock;
    KDPC Dpc;
    volatile uint16_t PendingIsr;

    NET_DEVICE NetDevice;
} RTL8139_DEVICE;


extern const HAL_API* gHal;
extern RTL8139_DEVICE gDevice;
extern bool gDevicePresent;

bool Rtl8139ReadBar(uint8_t bus, uint8_t dev, uint8_t fn, uint8_t index, RTL8139_BAR* out);
KSTATUS Rtl8139MapMmio(uint64_t physBase, volatile uint8_t** outMmio);
KSTATUS Rtl8139SelectRegisterBar(RTL8139_DEVICE* r);
void Rtl8139EnablePci(RTL8139_DEVICE* r);