add system time, clean up pci into pci.sys, clean up syscall names, fix USERAPC1 typo

code/public/ntlite/ddi/pci.h

@@ -0,0 +1,118 @@
+#pragma once
+// pci.h - PCI bus driver DDI exported by pci.sys
+//
+// Function drivers must not enumerate PCI or decode BARs themselves.  They bind
+// to PCI PDOs through the I/O manager and use these routines to access the PCI
+// function represented by their PDO.
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <ntlite/status.h>
+#include <ntlite/ddi/io_driver.h>
+
+#ifndef PCI_API
+#  ifdef PCI_SYS_BUILD
+#    define PCI_API __declspec(dllexport)
+#  else
+#    define PCI_API __declspec(dllimport)
+#  endif
+#endif
+
+
+typedef struct PCI_ADDRESS {
+    uint16_t Segment;
+    uint8_t  Bus;
+    uint8_t  Device;
+    uint8_t  Function;
+} PCI_ADDRESS;
+
+typedef struct PCI_DEVICE_INFO {
+    PCI_ADDRESS Address;
+
+    uint16_t VendorId;
+    uint16_t DeviceId;
+    uint16_t SubsystemVendorId;
+    uint16_t SubsystemId;
+
+    uint8_t RevisionId;
+    uint8_t ProgIf;
+    uint8_t Subclass;
+    uint8_t ClassCode;
+    uint8_t HeaderType;
+
+    uint8_t InterruptLine;
+    uint8_t InterruptPin;
+} PCI_DEVICE_INFO;
+
+typedef enum PCI_BAR_TYPE {
+    PciBarUnused = 0,
+    PciBarIo,
+    PciBarMemory32,
+    PciBarMemory64,
+} PCI_BAR_TYPE;
+
+typedef struct PCI_BAR {
+    PCI_BAR_TYPE Type;
+    uint8_t      Index;
+    uint64_t     Base;
+    uint64_t     Length;
+    bool         Prefetchable;
+} PCI_BAR;
+
+#define PCI_ENABLE_IO          0x00000001u
+#define PCI_ENABLE_MEMORY      0x00000002u
+#define PCI_ENABLE_BUSMASTER   0x00000004u
+#define PCI_ENABLE_INTX        0x00000008u
+#define PCI_DISABLE_INTX       0x00000010u
+
+#define PCI_CONFIG_VENDOR_DEVICE       0x00u
+#define PCI_CONFIG_COMMAND_STATUS      0x04u
+#define PCI_CONFIG_REVISION_CLASS      0x08u
+#define PCI_CONFIG_HEADER_TYPE         0x0Cu
+#define PCI_CONFIG_BAR0                0x10u
+#define PCI_CONFIG_INTERRUPT_LINE_PIN  0x3Cu
+
+PCI_API uint32_t PciDriverAbiVersion(void);
+
+PCI_API KSTATUS PciGetDeviceInfo(DEVICE_OBJECT* pdo,
+                                               PCI_DEVICE_INFO* outInfo);
+
+PCI_API KSTATUS PciReadConfig8(DEVICE_OBJECT* pdo,
+                                             uint16_t offset,
+                                             uint8_t* outValue);
+PCI_API KSTATUS PciReadConfig16(DEVICE_OBJECT* pdo,
+                                              uint16_t offset,
+                                              uint16_t* outValue);
+PCI_API KSTATUS PciReadConfig32(DEVICE_OBJECT* pdo,
+                                              uint16_t offset,
+                                              uint32_t* outValue);
+
+PCI_API KSTATUS PciWriteConfig8(DEVICE_OBJECT* pdo,
+                                              uint16_t offset,
+                                              uint8_t value);
+PCI_API KSTATUS PciWriteConfig16(DEVICE_OBJECT* pdo,
+                                               uint16_t offset,
+                                               uint16_t value);
+PCI_API KSTATUS PciWriteConfig32(DEVICE_OBJECT* pdo,
+                                               uint16_t offset,
+                                               uint32_t value);
+
+PCI_API KSTATUS PciGetBar(DEVICE_OBJECT* pdo,
+                                        uint8_t index,
+                                        PCI_BAR* outBar);
+
+PCI_API KSTATUS PciMapBar(DEVICE_OBJECT* pdo,
+                                        uint8_t index,
+                                        uint64_t pageFlags,
+                                        void** outVirtual,
+                                        uint64_t* outLength);
+
+PCI_API KSTATUS PciEnableDevice(DEVICE_OBJECT* pdo,
+                                              uint32_t flags);
+
+PCI_API KSTATUS PciGetInterrupt(DEVICE_OBJECT* pdo,
+                                              uint8_t* outIrq);
+
+PCI_API KSTATUS PciEnableMsi(DEVICE_OBJECT* pdo,
+                                           uint8_t irqSlot);