add system time, clean up pci into pci.sys, clean up syscall names, fix USERAPC1 typo
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maksw committed
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c1a291c4c9
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e41bf6e2c0
64 files changed
+4514
-2220
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@@ -27,22 +27,42 @@ typedef struct HAL_TIMER {
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uint8_t IrqNumber;
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} HAL_TIMER;
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typedef struct HAL_PCI {
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uint32_t (*Read32)(uint8_t bus, uint8_t dev,
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uint8_t fn, uint8_t reg);
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void (*Write32)(uint8_t bus, uint8_t dev,
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uint8_t fn, uint8_t reg, uint32_t val);
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bool (*FindDevice)(uint16_t vendor, uint16_t device,
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uint8_t* bus, uint8_t* dev, uint8_t* fn);
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bool (*FindClass)(uint8_t classCode, uint8_t subclass,
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uint8_t* bus, uint8_t* dev, uint8_t* fn);
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// Returns the IRQ line from PCI config space (register 0x3C, byte 0).
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// Returns 0xFF if no interrupt is wired.
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uint8_t (*GetIrqLine)(uint8_t bus, uint8_t dev, uint8_t fn);
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// Program a PCI MSI capability to deliver to vector (0x20 + irqSlot).
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// irqSlot must correspond to a kernel IRQ stub/vector slot.
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KSTATUS (*EnableMsi)(uint8_t bus, uint8_t dev, uint8_t fn, uint8_t irqSlot);
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#define HAL_RTC_TIME_FLAG_VALID 0x0001u
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#define HAL_RTC_TIME_FLAG_RTC 0x0002u
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typedef struct HAL_RTC_TIME {
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uint16_t Year;
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uint8_t Month;
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uint8_t Day;
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uint8_t Hour;
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uint8_t Minute;
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uint8_t Second;
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uint32_t Nanosecond;
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uint16_t Flags;
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uint16_t Reserved;
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} HAL_RTC_TIME;
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typedef struct HAL_RTC {
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KSTATUS (*QueryTime)(HAL_RTC_TIME* outTime);
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} HAL_RTC;
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typedef struct HAL_PCI {
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// Raw PCI configuration access. Policy-level operations such as
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// enumeration, BAR decoding, interrupt discovery, and MSI programming
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// belong to pci.sys.
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uint32_t (*Read32)(uint16_t segment,
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uint8_t bus,
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uint8_t dev,
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uint8_t fn,
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uint16_t offset);
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void (*Write32)(uint16_t segment,
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uint8_t bus,
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uint8_t dev,
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uint8_t fn,
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uint16_t offset,
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uint32_t value);
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} HAL_PCI;
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typedef struct HAL_INTC {
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@@ -63,6 +83,7 @@ typedef struct HAL_API {
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void *(*PhysToVirt)(uint64_t physAddr);
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HAL_SCREEN Screen;
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HAL_TIMER Timer;
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HAL_RTC Rtc;
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HAL_PCI Pci;
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HAL_INTC Intc;
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HAL_POWER Power;
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@@ -87,7 +108,7 @@ typedef struct HAL_INIT_PARAMS {
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void* (*AllocatePool)(size_t size);
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} HAL_INIT_PARAMS;
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#define HAL_API_VERSION 3
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#define HAL_API_VERSION 5
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__declspec(dllexport) const HAL_API* HalGetApi(void);
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__declspec(dllexport) void HalRegisterScheduler(void (*pKeSchedulerTick)(void));
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@@ -0,0 +1,118 @@
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#pragma once
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// pci.h - PCI bus driver DDI exported by pci.sys
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//
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// Function drivers must not enumerate PCI or decode BARs themselves. They bind
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// to PCI PDOs through the I/O manager and use these routines to access the PCI
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// function represented by their PDO.
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <ntlite/status.h>
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#include <ntlite/ddi/io_driver.h>
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#ifndef PCI_API
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# ifdef PCI_SYS_BUILD
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# define PCI_API __declspec(dllexport)
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# else
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# define PCI_API __declspec(dllimport)
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# endif
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#endif
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typedef struct PCI_ADDRESS {
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uint16_t Segment;
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uint8_t Bus;
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uint8_t Device;
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uint8_t Function;
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} PCI_ADDRESS;
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typedef struct PCI_DEVICE_INFO {
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PCI_ADDRESS Address;
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uint16_t VendorId;
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uint16_t DeviceId;
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uint16_t SubsystemVendorId;
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uint16_t SubsystemId;
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uint8_t RevisionId;
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uint8_t ProgIf;
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uint8_t Subclass;
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uint8_t ClassCode;
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uint8_t HeaderType;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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} PCI_DEVICE_INFO;
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typedef enum PCI_BAR_TYPE {
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PciBarUnused = 0,
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PciBarIo,
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PciBarMemory32,
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PciBarMemory64,
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} PCI_BAR_TYPE;
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typedef struct PCI_BAR {
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PCI_BAR_TYPE Type;
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uint8_t Index;
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uint64_t Base;
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uint64_t Length;
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bool Prefetchable;
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} PCI_BAR;
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#define PCI_ENABLE_IO 0x00000001u
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#define PCI_ENABLE_MEMORY 0x00000002u
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#define PCI_ENABLE_BUSMASTER 0x00000004u
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#define PCI_ENABLE_INTX 0x00000008u
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#define PCI_DISABLE_INTX 0x00000010u
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#define PCI_CONFIG_VENDOR_DEVICE 0x00u
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#define PCI_CONFIG_COMMAND_STATUS 0x04u
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#define PCI_CONFIG_REVISION_CLASS 0x08u
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#define PCI_CONFIG_HEADER_TYPE 0x0Cu
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#define PCI_CONFIG_BAR0 0x10u
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#define PCI_CONFIG_INTERRUPT_LINE_PIN 0x3Cu
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PCI_API uint32_t PciDriverAbiVersion(void);
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PCI_API KSTATUS PciGetDeviceInfo(DEVICE_OBJECT* pdo,
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PCI_DEVICE_INFO* outInfo);
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PCI_API KSTATUS PciReadConfig8(DEVICE_OBJECT* pdo,
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uint16_t offset,
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uint8_t* outValue);
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PCI_API KSTATUS PciReadConfig16(DEVICE_OBJECT* pdo,
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uint16_t offset,
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uint16_t* outValue);
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PCI_API KSTATUS PciReadConfig32(DEVICE_OBJECT* pdo,
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uint16_t offset,
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uint32_t* outValue);
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PCI_API KSTATUS PciWriteConfig8(DEVICE_OBJECT* pdo,
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uint16_t offset,
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uint8_t value);
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PCI_API KSTATUS PciWriteConfig16(DEVICE_OBJECT* pdo,
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uint16_t offset,
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uint16_t value);
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PCI_API KSTATUS PciWriteConfig32(DEVICE_OBJECT* pdo,
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uint16_t offset,
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uint32_t value);
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PCI_API KSTATUS PciGetBar(DEVICE_OBJECT* pdo,
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uint8_t index,
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PCI_BAR* outBar);
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PCI_API KSTATUS PciMapBar(DEVICE_OBJECT* pdo,
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uint8_t index,
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uint64_t pageFlags,
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void** outVirtual,
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uint64_t* outLength);
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PCI_API KSTATUS PciEnableDevice(DEVICE_OBJECT* pdo,
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uint32_t flags);
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PCI_API KSTATUS PciGetInterrupt(DEVICE_OBJECT* pdo,
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uint8_t* outIrq);
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PCI_API KSTATUS PciEnableMsi(DEVICE_OBJECT* pdo,
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uint8_t irqSlot);
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