parallel compile, SMP, swapgs, cleanup, remove useless Reserved fields

code/kernel/hal/hal_apic.c

@@ -2,18 +2,25 @@
 #include <kernel/hal/hal_apic.h>
 #include <ntlite/ddi/hal_api.h>
 #include <stdint.h>
+#include <intrin.h>
 
 extern HAL_API gApi;
 
 // ---- Local APIC ----
 static volatile uint32_t* gLapic = (volatile uint32_t *)0;
 #define LAPIC_REG(off)   (*(volatile uint32_t *)((uint8_t *)gLapic + (off)))
+#define LAPIC_ID         0x020
 #define LAPIC_EOI        0x0B0
 #define LAPIC_SPURIOUS   0x0F0
+#define LAPIC_ICR_LO     0x300
+#define LAPIC_ICR_HI     0x310
 #define LAPIC_ENABLE     0x100   // bit in spurious vector register
 
+#define APIC_VECTOR_RESCHEDULE   0xF0u
+
 // ---- I/O APIC ----
 static volatile uint32_t* gIoapic = (volatile uint32_t *)0;
+static uint32_t gBspLapicId = 0;
 #define IOAPIC_IDX   0x00
 #define IOAPIC_DATA  0x10
 
@@ -26,18 +33,99 @@ static void IoapicWrite(uint8_t reg, uint32_t val) {
     *(volatile uint32_t *)((uint8_t *)gIoapic + IOAPIC_DATA) = val;
 }
 
+
+static void HalApicStallFallback(uint32_t loops) {
+    for (volatile uint32_t i = 0; i < loops; i++) {
+        _mm_pause();
+    }
+}
+
+static void HalApicStallUs(uint32_t us) {
+    if (gApi.Timer.Stall) gApi.Timer.Stall(us);
+    else HalApicStallFallback(us * 128u + 1u);
+}
+
+static void HalApicWaitIcrIdle(void) {
+    for (uint32_t i = 0; i < 1000000u; i++) {
+        if (!(LAPIC_REG(LAPIC_ICR_LO) & (1u << 12)))
+            return;
+        _mm_pause();
+    }
+}
+
+static void HalApicSendIpi(uint32_t lapicId, uint32_t low) {
+    HalApicWaitIcrIdle();
+    LAPIC_REG(LAPIC_ICR_HI) = lapicId << 24;
+    LAPIC_REG(LAPIC_ICR_LO) = low;
+    HalApicWaitIcrIdle();
+}
+
 // IRQ n -> redirection table at register 0x10 + 2*n (low), 0x11 + 2*n (high).
 #define IOREDTBL_LO(n)  (0x10 + 2*(n))
 #define IOREDTBL_HI(n)  (0x11 + 2*(n))
 // Interrupt vector base: IRQ 0 -> vector 0x20, IRQ 1 -> 0x21, ...
 #define IRQ_VECTOR_BASE  0x20
 
+__declspec(dllexport) uint32_t HalGetBspLapicId(void) {
+    return gBspLapicId;
+}
+
+__declspec(dllexport) void HalApicEnableCurrentCpu(void) {
+    if (!gLapic) return;
+    LAPIC_REG(LAPIC_SPURIOUS) = LAPIC_ENABLE | 0xFF;
+}
+
+
+__declspec(dllexport) void HalApicSendPanicIpi(void) {
+    if (!gLapic) return;
+
+    // Stop-the-world panic IPI.  Use NMI delivery instead of a normal fixed
+    // vector so CPUs running with IF=0 inside spinlock/high-IRQL regions still
+    // enter the panic path.  The NMI vector is already installed in the IDT on
+    // every CPU that has reached kernel-owned state.
+    HalApicWaitIcrIdle();
+    LAPIC_REG(LAPIC_ICR_HI) = 0;
+    LAPIC_REG(LAPIC_ICR_LO) = (3u << 18) | (4u << 8); // all-excluding-self, NMI
+    HalApicWaitIcrIdle();
+}
+
+__declspec(dllexport) void HalApicSendRescheduleIpi(uint32_t lapicId) {
+    if (!gLapic) return;
+    HalApicSendIpi(lapicId, APIC_VECTOR_RESCHEDULE); // fixed delivery, physical destination
+}
+
+__declspec(dllexport) void HalApicSendTlbShootdownIpi(uint32_t lapicId) {
+    if (!gLapic) return;
+
+    // TLB shootdown must reach CPUs that may be spinning with IF=0 inside
+    // high-IRQL/spinlock regions, so use NMI delivery rather than a fixed
+    // vector.  The NMI stub handles active shootdowns and returns; unexpected
+    // NMIs still go through the normal fault/panic path.
+    HalApicSendIpi(lapicId, (4u << 8)); // NMI delivery, physical destination
+}
+
+__declspec(dllexport) KSTATUS HalStartApplicationProcessor(uint32_t lapicId, uint8_t startupVector) {
+    if (!gLapic || !startupVector || lapicId == gBspLapicId)
+        return STATUS_INVALID_PARAMETER;
+
+    // INIT assert/deassert, then two SIPIs.  The target begins at startupVector << 12.
+    HalApicSendIpi(lapicId, 0x0000C500u); // INIT, level assert, level-triggered
+    HalApicStallUs(10000);
+    HalApicSendIpi(lapicId, 0x00008500u); // INIT, level deassert
+    HalApicStallUs(200);
+    HalApicSendIpi(lapicId, 0x00000600u | startupVector); // SIPI
+    HalApicStallUs(200);
+    HalApicSendIpi(lapicId, 0x00000600u | startupVector); // SIPI retry
+    HalApicStallUs(200);
+    return STATUS_SUCCESS;
+}
+
 void HalApicRouteIrq(uint8_t irq) {
     // Full initial setup of the redirection entry.
     // Sets the vector and clears the mask bit in one write.
     uint32_t vector = IRQ_VECTOR_BASE + irq;   // e.g. IRQ 1 -> vector 0x21
+    IoapicWrite(IOREDTBL_HI(irq), gBspLapicId << 24); // external IRQs target the BSP
     IoapicWrite(IOREDTBL_LO(irq), vector);     // unmasked (bit 16 = 0), edge, fixed
-    IoapicWrite(IOREDTBL_HI(irq), 0);          // deliver to LAPIC id 0
 }
 
 void HalApicMaskIrq(uint8_t irq) {
@@ -50,8 +138,8 @@ void HalApicUnmaskIrq(uint8_t irq) {
     uint32_t lo = IoapicRead(IOREDTBL_LO(irq));
     lo &= ~(1 << 16);   // clear mask bit
     lo  =  (lo & ~0xFF) | (IRQ_VECTOR_BASE + irq);
+    IoapicWrite(IOREDTBL_HI(irq), gBspLapicId << 24);
     IoapicWrite(IOREDTBL_LO(irq), lo);
-    IoapicWrite(IOREDTBL_HI(irq), 0);   // LAPIC id 0
 }
 
 void HalApicSendEoi(void) {
@@ -62,6 +150,10 @@ void HalApicInitialize(uintptr_t lapicPhys, uintptr_t ioapicPhys) {
     gLapic  = (volatile uint32_t *)(gApi.PhysToVirt(lapicPhys));
     gIoapic = (volatile uint32_t *)(gApi.PhysToVirt(ioapicPhys));
 
+    // The BSP is the CPU executing HAL init. Keep all external/device IRQs
+    // routed to this LAPIC; CPU-local IPIs use the local APIC directly.
+    gBspLapicId = (LAPIC_REG(LAPIC_ID) >> 24) & 0xFF;
+
     // Enable Local APIC, set spurious vector to 0xFF.
     LAPIC_REG(LAPIC_SPURIOUS) = LAPIC_ENABLE | 0xFF;
 
@@ -69,6 +161,6 @@ void HalApicInitialize(uintptr_t lapicPhys, uintptr_t ioapicPhys) {
     uint32_t maxRedir = (IoapicRead(1) >> 16) & 0xFF;
     for (uint8_t i = 0; i <= maxRedir; i++) {
         IoapicWrite(IOREDTBL_LO(i), (1 << 16) | (IRQ_VECTOR_BASE + i));
-        IoapicWrite(IOREDTBL_HI(i), 0);
+        IoapicWrite(IOREDTBL_HI(i), gBspLapicId << 24);
     }
 }