move keyboard and mouse out of HAL into a standalone ps2.sys driver, implement usb stack with xhci controller discovery, hid keyboard/mouse, and bulk-only mass storage, add pci msi support with capability chain walking and software irq vector allocation (slots 16-23), rewrite user virtual memory as a USER_VA_REGION descriptor arena with per-process ownership tracking and guard page support, replacing the old bump allocator and top-down image region, add MmCreateUserRegion/MmDestroyAllUserRegions so process teardown reclaims all user va in one pass, allocate a pool-backed shadow framebuffer in hal_screen to fix cursor tearing and scroll corruption, reserve ap trampoline page below 1mb in uefi bootloader before boot services exit, rewrite memset/memcpy/memmove/memcmp with __stosq/__movsq intrinsics, promote driver flag literals to macros and add multi-tu STANDALONE_DRIVERS table to build.c, split rtl8139/rtl816x into header+source, rename KbReadScancode to KbReadKey, improve page fault output with MmDebugDescribeAddress and user region dump, fix %p to %016llX throughout.
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@@ -16,11 +16,23 @@ static volatile uint32_t* gLapic = (volatile uint32_t *)0;
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#define LAPIC_ICR_HI 0x310
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#define LAPIC_ENABLE 0x100 // bit in spurious vector register
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#define IA32_APIC_BASE 0x0000001Bu
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#define IA32_APIC_BASE_ENABLE (1ULL << 11)
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#define IA32_APIC_BASE_X2APIC (1ULL << 10)
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#define IA32_X2APIC_ID 0x00000802u
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#define IA32_X2APIC_EOI 0x0000080Bu
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#define IA32_X2APIC_SVR 0x0000080Fu
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#define IA32_X2APIC_ICR 0x00000830u
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#define CPUID_FEATURE_ECX_X2APIC (1u << 21)
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#define APIC_VECTOR_RESCHEDULE 0xF0u
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// ---- I/O APIC ----
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static volatile uint32_t* gIoapic = (volatile uint32_t *)0;
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static uint32_t gBspLapicId = 0;
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static uint8_t gX2ApicSupported = 0;
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static uint8_t gX2ApicEnabled = 0;
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#define IOAPIC_IDX 0x00
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#define IOAPIC_DATA 0x10
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@@ -33,6 +45,14 @@ static void IoapicWrite(uint8_t reg, uint32_t val) {
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*(volatile uint32_t *)((uint8_t *)gIoapic + IOAPIC_DATA) = val;
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}
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static void HalApicDetectMode(void) {
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int regs[4] = {0, 0, 0, 0};
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__cpuid(regs, 1);
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gX2ApicSupported = (regs[2] & CPUID_FEATURE_ECX_X2APIC) ? 1u : 0u;
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uint64_t apicBase = __readmsr(IA32_APIC_BASE);
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gX2ApicEnabled = (gX2ApicSupported && (apicBase & IA32_APIC_BASE_X2APIC)) ? 1u : 0u;
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}
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static void HalApicStallFallback(uint32_t loops) {
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for (volatile uint32_t i = 0; i < loops; i++) {
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@@ -46,6 +66,9 @@ static void HalApicStallUs(uint32_t us) {
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}
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static void HalApicWaitIcrIdle(void) {
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if (gX2ApicEnabled)
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return;
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for (uint32_t i = 0; i < 1000000u; i++) {
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if (!(LAPIC_REG(LAPIC_ICR_LO) & (1u << 12)))
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return;
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@@ -54,6 +77,11 @@ static void HalApicWaitIcrIdle(void) {
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}
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static void HalApicSendIpi(uint32_t lapicId, uint32_t low) {
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if (gX2ApicEnabled) {
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__writemsr(IA32_X2APIC_ICR, ((uint64_t)lapicId << 32) | low);
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return;
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}
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HalApicWaitIcrIdle();
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LAPIC_REG(LAPIC_ICR_HI) = lapicId << 24;
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LAPIC_REG(LAPIC_ICR_LO) = low;
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@@ -63,52 +91,70 @@ static void HalApicSendIpi(uint32_t lapicId, uint32_t low) {
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// IRQ n -> redirection table at register 0x10 + 2*n (low), 0x11 + 2*n (high).
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#define IOREDTBL_LO(n) (0x10 + 2*(n))
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#define IOREDTBL_HI(n) (0x11 + 2*(n))
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// Interrupt vector base: IRQ 0 -> vector 0x20, IRQ 1 -> 0x21, ...
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// Interrupt vector base: IRQ 0 -> vector 0x20, IRQ 1 -> vector 0x21, ...
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#define IRQ_VECTOR_BASE 0x20
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__declspec(dllexport) uint32_t HalGetBspLapicId(void) {
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return gBspLapicId;
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}
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__declspec(dllexport) void HalApicEnableCurrentCpu(void) {
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if (!gLapic) return;
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LAPIC_REG(LAPIC_SPURIOUS) = LAPIC_ENABLE | 0xFF;
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__declspec(dllexport) uint8_t HalApicUsingX2Apic(void) {
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return gX2ApicEnabled;
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}
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__declspec(dllexport) uint8_t HalApicCanAddressId(uint32_t lapicId) {
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if (gX2ApicEnabled)
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return 1u;
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return (lapicId < 256u) ? 1u : 0u;
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}
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__declspec(dllexport) void HalApicEnableCurrentCpu(void) {
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uint64_t apicBase = __readmsr(IA32_APIC_BASE) | IA32_APIC_BASE_ENABLE;
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if (gX2ApicEnabled) {
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apicBase |= IA32_APIC_BASE_X2APIC;
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__writemsr(IA32_APIC_BASE, apicBase);
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__writemsr(IA32_X2APIC_SVR, LAPIC_ENABLE | 0xFFu);
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return;
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}
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__writemsr(IA32_APIC_BASE, apicBase);
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if (gLapic)
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LAPIC_REG(LAPIC_SPURIOUS) = LAPIC_ENABLE | 0xFF;
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}
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__declspec(dllexport) void HalApicSendPanicIpi(void) {
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if (!gLapic) return;
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if (!gLapic && !gX2ApicEnabled) return;
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// Stop-the-world panic IPI. Use NMI delivery instead of a normal fixed
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// Stop-the-world panic IPI. Use NMI delivery instead of a normal fixed
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// vector so CPUs running with IF=0 inside spinlock/high-IRQL regions still
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// enter the panic path. The NMI vector is already installed in the IDT on
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// enter the panic path. The NMI vector is already installed in the IDT on
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// every CPU that has reached kernel-owned state.
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HalApicWaitIcrIdle();
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LAPIC_REG(LAPIC_ICR_HI) = 0;
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LAPIC_REG(LAPIC_ICR_LO) = (3u << 18) | (4u << 8); // all-excluding-self, NMI
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HalApicWaitIcrIdle();
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HalApicSendIpi(0, (3u << 18) | (4u << 8)); // all-excluding-self, NMI
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}
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__declspec(dllexport) void HalApicSendRescheduleIpi(uint32_t lapicId) {
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if (!gLapic) return;
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if (!gLapic && !gX2ApicEnabled) return;
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HalApicSendIpi(lapicId, APIC_VECTOR_RESCHEDULE); // fixed delivery, physical destination
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}
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__declspec(dllexport) void HalApicSendTlbShootdownIpi(uint32_t lapicId) {
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if (!gLapic) return;
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if (!gLapic && !gX2ApicEnabled) return;
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// TLB shootdown must reach CPUs that may be spinning with IF=0 inside
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// high-IRQL/spinlock regions, so use NMI delivery rather than a fixed
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// vector. The NMI stub handles active shootdowns and returns; unexpected
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// vector. The NMI stub handles active shootdowns and returns; unexpected
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// NMIs still go through the normal fault/panic path.
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HalApicSendIpi(lapicId, (4u << 8)); // NMI delivery, physical destination
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}
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__declspec(dllexport) KSTATUS HalStartApplicationProcessor(uint32_t lapicId, uint8_t startupVector) {
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if (!gLapic || !startupVector || lapicId == gBspLapicId)
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if ((!gLapic && !gX2ApicEnabled) || !startupVector || lapicId == gBspLapicId)
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return STATUS_INVALID_PARAMETER;
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if (!HalApicCanAddressId(lapicId))
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return STATUS_NOT_SUPPORTED;
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// INIT assert/deassert, then two SIPIs. The target begins at startupVector << 12.
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// INIT assert/deassert, then two SIPIs. The target begins at startupVector << 12.
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HalApicSendIpi(lapicId, 0x0000C500u); // INIT, level assert, level-triggered
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HalApicStallUs(10000);
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HalApicSendIpi(lapicId, 0x00008500u); // INIT, level deassert
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@@ -124,7 +170,7 @@ void HalApicRouteIrq(uint8_t irq) {
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// Full initial setup of the redirection entry.
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// Sets the vector and clears the mask bit in one write.
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uint32_t vector = IRQ_VECTOR_BASE + irq; // e.g. IRQ 1 -> vector 0x21
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IoapicWrite(IOREDTBL_HI(irq), gBspLapicId << 24); // external IRQs target the BSP
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IoapicWrite(IOREDTBL_HI(irq), (gBspLapicId & 0xFFu) << 24); // external IRQs target the BSP
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IoapicWrite(IOREDTBL_LO(irq), vector); // unmasked (bit 16 = 0), edge, fixed
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}
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@@ -138,29 +184,37 @@ void HalApicUnmaskIrq(uint8_t irq) {
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uint32_t lo = IoapicRead(IOREDTBL_LO(irq));
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lo &= ~(1 << 16); // clear mask bit
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lo = (lo & ~0xFF) | (IRQ_VECTOR_BASE + irq);
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IoapicWrite(IOREDTBL_HI(irq), gBspLapicId << 24);
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IoapicWrite(IOREDTBL_HI(irq), (gBspLapicId & 0xFFu) << 24);
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IoapicWrite(IOREDTBL_LO(irq), lo);
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}
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void HalApicSendEoi(void) {
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if (gX2ApicEnabled) {
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__writemsr(IA32_X2APIC_EOI, 0);
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return;
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}
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LAPIC_REG(LAPIC_EOI) = 0;
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}
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void HalApicInitialize(uintptr_t lapicPhys, uintptr_t ioapicPhys) {
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HalApicDetectMode();
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gLapic = (volatile uint32_t *)(gApi.PhysToVirt(lapicPhys));
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gIoapic = (volatile uint32_t *)(gApi.PhysToVirt(ioapicPhys));
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// The BSP is the CPU executing HAL init. Keep all external/device IRQs
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// routed to this LAPIC; CPU-local IPIs use the local APIC directly.
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gBspLapicId = (LAPIC_REG(LAPIC_ID) >> 24) & 0xFF;
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if (gX2ApicEnabled)
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gBspLapicId = (uint32_t)__readmsr(IA32_X2APIC_ID);
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else
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gBspLapicId = (LAPIC_REG(LAPIC_ID) >> 24) & 0xFF;
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// Enable Local APIC, set spurious vector to 0xFF.
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LAPIC_REG(LAPIC_SPURIOUS) = LAPIC_ENABLE | 0xFF;
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HalApicEnableCurrentCpu();
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// Mask all IOAPIC lines initially.
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uint32_t maxRedir = (IoapicRead(1) >> 16) & 0xFF;
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for (uint8_t i = 0; i <= maxRedir; i++) {
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IoapicWrite(IOREDTBL_LO(i), (1 << 16) | (IRQ_VECTOR_BASE + i));
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IoapicWrite(IOREDTBL_HI(i), gBspLapicId << 24);
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IoapicWrite(IOREDTBL_HI(i), (gBspLapicId & 0xFFu) << 24);
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}
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}
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