move keyboard and mouse out of HAL into a standalone ps2.sys driver, implement usb stack with xhci controller discovery, hid keyboard/mouse, and bulk-only mass storage, add pci msi support with capability chain walking and software irq vector allocation (slots 16-23), rewrite user virtual memory as a USER_VA_REGION descriptor arena with per-process ownership tracking and guard page support, replacing the old bump allocator and top-down image region, add MmCreateUserRegion/MmDestroyAllUserRegions so process teardown reclaims all user va in one pass, allocate a pool-backed shadow framebuffer in hal_screen to fix cursor tearing and scroll corruption, reserve ap trampoline page below 1mb in uefi bootloader before boot services exit, rewrite memset/memcpy/memmove/memcmp with __stosq/__movsq intrinsics, promote driver flag literals to macros and add multi-tu STANDALONE_DRIVERS table to build.c, split rtl8139/rtl816x into header+source, rename KbReadScancode to KbReadKey, improve page fault output with MmDebugDescribeAddress and user region dump, fix %p to %016llX throughout.
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@@ -1,130 +1,26 @@
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// ide.c — IDE/ATA driver: PIO (sync fallback) + Bus Master DMA (async)
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//
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// Architecture
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// ------------
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// The dispatch path mirrors AHCI:
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// IoCallDriver → IdeDispatchReadWrite → IRP queue or inline PIO
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// IdeWorker → dequeues IRP, calls IdeDmaRw(), completes the IRP
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// IdeIsr → clears BM status, queues a DPC
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// IdeDpc → signals gDmaEvent to unblock the worker
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//
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// Graceful degradation: if Bus Master init fails (no PCI IDE controller,
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// BAR4 not assigned, PRDT allocation above 4 GB, etc.) the same device
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// object remains registered and dispatch completes IRPs inline through PIO.
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//
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// PRDT layout
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// -----------
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// One page allocated via MmAllocateContiguous. We build up to PRDT_MAX_ENTRIES
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// entries by walking the transfer buffer in page-sized chunks and looking up
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// each page's physical address via MmGetPhysicalAddress. Adjacent physical
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// pages are coalesced into a single PRD entry where possible.
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//
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// LBA48 vs LBA28
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// --------------
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// DMA commands exist in both modes: CMD_READ/WRITE_DMA_EXT (0x25/0x35) for
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// LBA48 and CMD_READ/WRITE_DMA (0xC8/0xCA) for LBA28. The existing
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// gSupportsLba48 flag picks the right variant.
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#include <stdint.h>
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#include <string.h>
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#include <intrin.h>
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#include <ntlite/ddi/io_driver.h>
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#include <ntlite/ddi/hal_api.h>
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#include <kernel/ke_debug.h>
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#include <kernel/ke_sched.h>
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#include <kernel/ke_irp.h>
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#include <kernel/ke_event.h>
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#include <kernel/ke_semaphore.h>
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#include <kernel/ke_thread.h>
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#include <kernel/ke_irq.h>
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#include <kernel/ke_dpc.h>
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#include <kernel/mm_phys.h>
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#include <kernel/mm_virt.h>
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// ---------------------------------------------------------------------------
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// IDE register map (primary channel, base 0x1F0)
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// ---------------------------------------------------------------------------
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#define IDE_DATA 0x1F0
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#define IDE_ERR 0x1F1
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#define IDE_SECCNT 0x1F2
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#define IDE_LBA0 0x1F3
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#define IDE_LBA1 0x1F4
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#define IDE_LBA2 0x1F5
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#define IDE_DRIVE 0x1F6
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#define IDE_STATUS 0x1F7
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#define IDE_CMD 0x1F7
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#define IDE_ALT 0x3F6
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#define IDE_BUSY 0x80
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#define IDE_READY 0x40
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#define IDE_ERR_F 0x01
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#define IDE_DRQ 0x08
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// ATA commands
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#define CMD_READ_EXT 0x24 // PIO 48-bit read
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#define CMD_WRITE_EXT 0x34 // PIO 48-bit write
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#define CMD_READ_DMA_EXT 0x25 // DMA 48-bit read
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#define CMD_WRITE_DMA_EXT 0x35 // DMA 48-bit write
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#define CMD_READ_DMA 0xC8 // DMA 28-bit read
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#define CMD_WRITE_DMA 0xCA // DMA 28-bit write
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#define CMD_IDENT 0xEC
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// IDE primary IRQ
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#define IDE_IRQ_PRIMARY 14
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// ---------------------------------------------------------------------------
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// Bus Master IDE register offsets (relative to gBmBase, primary channel)
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// ---------------------------------------------------------------------------
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#define BM_CMD_REG 0x00 // command
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#define BM_STATUS_REG 0x02 // status
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#define BM_PRDT_REG 0x04 // PRDT physical address (32-bit)
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// BM_CMD_REG bits
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#define BM_CMD_START 0x01 // start DMA transfer
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#define BM_CMD_READ 0x08 // 1 = disk→memory (read), 0 = memory→disk (write)
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// BM_STATUS_REG bits
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#define BM_STATUS_ACTIVE 0x01 // DMA active
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#define BM_STATUS_ERROR 0x02 // DMA error (write 1 to clear)
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#define BM_STATUS_IRQ 0x04 // interrupt pending (write 1 to clear)
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// ---------------------------------------------------------------------------
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// Physical Region Descriptor (PRDT entry, 8 bytes)
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// The PRDT itself must not cross a 64 KB boundary and must be 4-byte aligned.
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// We allocate a full page so both constraints are trivially satisfied.
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// ---------------------------------------------------------------------------
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#pragma pack(push, 1)
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typedef struct {
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uint32_t physAddr; // physical base of this memory region
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uint16_t byteCount; // byte count; 0 means 64 KB
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uint16_t flags; // bit 15: End Of Table
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} PRD;
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#pragma pack(pop)
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#define PRD_EOT 0x8000u
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// 512 entries × 8 bytes = 4096 bytes = exactly one page; supports 512×64 KB = 32 MB
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#define PRDT_MAX_ENTRIES 512
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// ide.c - IDE/ATA disk I/O path and DriverEntry.
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#include "ide.h"
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// ---------------------------------------------------------------------------
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// Module state
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// ---------------------------------------------------------------------------
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static const HAL_API *gHal;
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static DRIVER_OBJECT gDriver;
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static DEVICE_OBJECT *gDevice = NULL;
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static bool gDmaEnabled = false;
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static uint64_t gSectorCount = 0;
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static bool gSupportsLba48 = false;
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const HAL_API *gHal;
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DRIVER_OBJECT gDriver;
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DEVICE_OBJECT *gDevice = NULL;
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bool gDmaEnabled = false;
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uint64_t gSectorCount = 0;
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bool gSupportsLba48 = false;
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// DMA hardware state
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static uint16_t gBmBase = 0; // Bus Master I/O base port (BAR4 & ~3)
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static PRD *gPrdtVirt = NULL; // kernel VA of PRDT page
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static uint32_t gPrdtPhys = 0; // 32-bit physical address of PRDT
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uint16_t gBmBase = 0; // Bus Master I/O base port (BAR4 & ~3)
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PRD *gPrdtVirt = NULL; // kernel VA of PRDT page
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uint32_t gPrdtPhys = 0; // 32-bit physical address of PRDT
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// Async worker synchronisation
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static IRP_QUEUE gIrpQueue;
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static SEMAPHORE *gIrpSemaphore = NULL;
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static EVENT *gDmaEvent = NULL; // auto-reset; DPC signals after each xfer
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static KDPC gDmaDpc; // bottom half for DMA completion
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IRP_QUEUE gIrpQueue;
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SEMAPHORE *gIrpSemaphore = NULL;
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EVENT *gDmaEvent = NULL; // auto-reset; DPC signals after each xfer
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KDPC gDmaDpc; // bottom half for DMA completion
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// ---------------------------------------------------------------------------
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// Bus Master I/O helpers
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@@ -255,7 +151,7 @@ static uint32_t BuildPrdt(void *virtBuf, uint32_t byteLen) {
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PHYSICAL_ADDRESS phys = MmGetPhysicalAddress(va);
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if (phys >> 32) {
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// Physical address above 4 GB — BM IDE's 32-bit PRDT can't reach it.
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DbgPrint("IDE DMA: buffer page at VA 0x%llx has phys 0x%llx > 4 GB\n",
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DbgPrint("IDE DMA: buffer page at VA 0x%016llX has phys 0x%016llX > 4 GB\n",
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(uint64_t)va, (uint64_t)phys);
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return 0;
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}
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@@ -294,7 +190,7 @@ static uint32_t BuildPrdt(void *virtBuf, uint32_t byteLen) {
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// IDE DMA completion DPC. The ISR owns hardware acknowledgement; this bottom
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// half wakes the worker outside hard IRQ/DIRQL context.
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// ---------------------------------------------------------------------------
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static void IdeDmaCompletionDpc(KDPC *dpc, void *context,
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void IdeDmaCompletionDpc(KDPC *dpc, void *context,
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void *systemArgument1, void *systemArgument2) {
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(void)dpc;
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(void)context;
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@@ -312,7 +208,7 @@ static void IdeDmaCompletionDpc(KDPC *dpc, void *context,
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// interrupt bits here and queue a DPC to wake the worker thread.
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// The worker reads the final status and fires IRP completion hooks.
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// ---------------------------------------------------------------------------
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static void IdeIsr(void) {
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void IdeIsr(void) {
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uint8_t bmSt = BmRead8(BM_STATUS_REG);
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if (!(bmSt & BM_STATUS_IRQ))
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return; // not our interrupt (spurious or secondary channel)
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@@ -417,7 +313,7 @@ static KSTATUS IdeDmaRw(uint64_t lba, uint32_t count, void *buf, bool write) {
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// Blocks on gIrpSemaphore. Each IrpQueueEnqueue increments it by one, so
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// the worker wakes once per submitted IRP. Mirrors AhciWorker exactly.
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// ---------------------------------------------------------------------------
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static void IdeWorker(uintptr_t arg) {
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void IdeWorker(uintptr_t arg) {
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(void)arg;
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while (true) {
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KeWaitSemaphore(gIrpSemaphore);
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@@ -473,90 +369,6 @@ static KSTATUS IdeDispatchReadWrite(DEVICE_OBJECT *device, IRP *irp) {
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// Returns true on success. On any failure, logs a message and returns false;
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// dispatch will complete IRPs inline through PIO.
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// ---------------------------------------------------------------------------
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static bool IdeDmaInit(void) {
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// ---- Find PCI IDE controller (class 0x01, subclass 0x01) --------------
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uint8_t bus, dev, fn;
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if (!gHal->Pci.FindClass(0x01, 0x01, &bus, &dev, &fn)) {
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DbgPrint("IDE DMA: No PCI IDE controller found — using PIO\n");
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return false;
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}
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// ---- Read BAR4 (Bus Master base, I/O space) ---------------------------
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// PCI config offset 0x20. Bit 0 must be 1 for I/O BAR.
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uint32_t bar4 = gHal->Pci.Read32(bus, dev, fn, 0x20);
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if (!(bar4 & 0x1)) {
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DbgPrint("IDE DMA: BAR4 is a memory BAR (0x%08x) — unexpected, using PIO\n", bar4);
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return false;
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}
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uint16_t bmBase = (uint16_t)(bar4 & 0xFFFC);
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if (bmBase == 0) {
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DbgPrint("IDE DMA: BAR4 is zero (firmware didn't assign it) — using PIO\n");
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return false;
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}
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DbgPrint("IDE DMA: Bus Master base = 0x%04X (bus %u, dev %u, fn %u)\n",
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bmBase, bus, dev, fn);
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// ---- Enable Bus Mastering in PCI Command register (bit 2) ------------
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uint32_t pciCmd = gHal->Pci.Read32(bus, dev, fn, 0x04);
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gHal->Pci.Write32(bus, dev, fn, 0x04, pciCmd | (1u << 2));
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// ---- Allocate PRDT page (must be 32-bit physical, 4-byte aligned) ----
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PHYSICAL_ADDRESS prdtPhys = MmAllocateContiguous(1);
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if (!prdtPhys) {
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DbgPrint("IDE DMA: Failed to allocate PRDT page\n");
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return false;
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}
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if (prdtPhys >> 32) {
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// MmAllocateContiguous returned memory above 4 GB — BM IDE can't
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// address it. This shouldn't happen on normal x86 systems with early
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// boot allocations but we check defensively.
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DbgPrint("IDE DMA: PRDT page is above 4 GB (0x%llx) — using PIO\n",
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(uint64_t)prdtPhys);
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return false;
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}
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void *prdtVirt = gHal->PhysToVirt(prdtPhys);
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DbgPrint("IDE DMA: PRDT at phys 0x%08x, virt %p\n", (uint32_t)prdtPhys, prdtVirt);
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// ---- Create synchronisation objects ------------------------------------
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SEMAPHORE *sem = NULL;
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if (!KSUCCESS(KeSemaphoreCreate(0, 0x7FFFFFFF, &sem))) {
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DbgPrint("IDE DMA: Failed to create IRP semaphore\n");
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return false;
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}
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EVENT *dmaEv = NULL;
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if (!KSUCCESS(KeEventCreate(EventAutoReset, 0, &dmaEv))) {
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DbgPrint("IDE DMA: Failed to create DMA completion event\n");
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return false;
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}
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// ---- Commit module state -----------------------------------------------
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gBmBase = bmBase;
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gPrdtPhys = (uint32_t)prdtPhys;
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gPrdtVirt = (PRD *)prdtVirt;
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gIrpSemaphore = sem;
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gDmaEvent = dmaEv;
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KeInitializeDpc(&gDmaDpc, IdeDmaCompletionDpc, (void *)0);
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IrpQueueInit(&gIrpQueue, sem);
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// ---- Register IRQ 14 --------------------------------------------------
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KeIrqRegister(IDE_IRQ_PRIMARY, IdeIsr);
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DbgPrint("IDE DMA: IRQ %u registered\n", IDE_IRQ_PRIMARY);
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// ---- Spawn worker thread -----------------------------------------------
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KSTATUS st = KeCreateKernelThread((uintptr_t)IdeWorker, 0,
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PriorityHigh, (THREAD **)NULL);
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if (!KSUCCESS(st)) {
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DbgPrint("IDE DMA: Worker thread creation failed (0x%x)\n", st);
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// Not fatal for init — the PRDT/IRQ are live but async callers will
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// never get completions. Better to surface the failure clearly.
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return false;
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}
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DbgPrint("IDE DMA: Init complete\n");
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return true;
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}
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// ---------------------------------------------------------------------------
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// DriverEntry
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@@ -0,0 +1,102 @@
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// ide.h - shared IDE/ATA driver internals.
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#pragma once
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#include <stdint.h>
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#include <string.h>
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#include <intrin.h>
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#include <ntlite/ddi/io_driver.h>
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#include <ntlite/ddi/hal_api.h>
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#include <kernel/ke_debug.h>
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#include <kernel/ke_sched.h>
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#include <kernel/ke_irp.h>
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#include <kernel/ke_event.h>
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#include <kernel/ke_semaphore.h>
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#include <kernel/ke_thread.h>
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#include <kernel/ke_irq.h>
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#include <kernel/ke_dpc.h>
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#include <kernel/mm_phys.h>
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#include <kernel/mm_virt.h>
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// ---------------------------------------------------------------------------
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// IDE register map (primary channel, base 0x1F0)
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// ---------------------------------------------------------------------------
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#define IDE_DATA 0x1F0
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#define IDE_ERR 0x1F1
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#define IDE_SECCNT 0x1F2
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#define IDE_LBA0 0x1F3
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#define IDE_LBA1 0x1F4
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#define IDE_LBA2 0x1F5
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#define IDE_DRIVE 0x1F6
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#define IDE_STATUS 0x1F7
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#define IDE_CMD 0x1F7
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#define IDE_ALT 0x3F6
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#define IDE_BUSY 0x80
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#define IDE_READY 0x40
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#define IDE_ERR_F 0x01
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#define IDE_DRQ 0x08
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// ATA commands
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#define CMD_READ_EXT 0x24 // PIO 48-bit read
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#define CMD_WRITE_EXT 0x34 // PIO 48-bit write
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#define CMD_READ_DMA_EXT 0x25 // DMA 48-bit read
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#define CMD_WRITE_DMA_EXT 0x35 // DMA 48-bit write
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#define CMD_READ_DMA 0xC8 // DMA 28-bit read
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#define CMD_WRITE_DMA 0xCA // DMA 28-bit write
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#define CMD_IDENT 0xEC
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// IDE primary IRQ
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#define IDE_IRQ_PRIMARY 14
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// ---------------------------------------------------------------------------
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// Bus Master IDE register offsets (relative to gBmBase, primary channel)
|
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// ---------------------------------------------------------------------------
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||||
#define BM_CMD_REG 0x00 // command
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#define BM_STATUS_REG 0x02 // status
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#define BM_PRDT_REG 0x04 // PRDT physical address (32-bit)
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// BM_CMD_REG bits
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#define BM_CMD_START 0x01 // start DMA transfer
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#define BM_CMD_READ 0x08 // 1 = disk→memory (read), 0 = memory→disk (write)
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// BM_STATUS_REG bits
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#define BM_STATUS_ACTIVE 0x01 // DMA active
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#define BM_STATUS_ERROR 0x02 // DMA error (write 1 to clear)
|
||||
#define BM_STATUS_IRQ 0x04 // interrupt pending (write 1 to clear)
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||||
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||||
// ---------------------------------------------------------------------------
|
||||
// Physical Region Descriptor (PRDT entry, 8 bytes)
|
||||
// The PRDT itself must not cross a 64 KB boundary and must be 4-byte aligned.
|
||||
// We allocate a full page so both constraints are trivially satisfied.
|
||||
// ---------------------------------------------------------------------------
|
||||
#pragma pack(push, 1)
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||||
typedef struct {
|
||||
uint32_t physAddr; // physical base of this memory region
|
||||
uint16_t byteCount; // byte count; 0 means 64 KB
|
||||
uint16_t flags; // bit 15: End Of Table
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||||
} PRD;
|
||||
#pragma pack(pop)
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||||
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||||
#define PRD_EOT 0x8000u
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||||
// 512 entries × 8 bytes = 4096 bytes = exactly one page; supports 512×64 KB = 32 MB
|
||||
#define PRDT_MAX_ENTRIES 512
|
||||
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||||
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||||
extern const HAL_API *gHal;
|
||||
extern DRIVER_OBJECT gDriver;
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||||
extern DEVICE_OBJECT *gDevice;
|
||||
extern bool gDmaEnabled;
|
||||
extern uint64_t gSectorCount;
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||||
extern bool gSupportsLba48;
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||||
extern uint16_t gBmBase;
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||||
extern PRD *gPrdtVirt;
|
||||
extern uint32_t gPrdtPhys;
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||||
extern IRP_QUEUE gIrpQueue;
|
||||
extern SEMAPHORE *gIrpSemaphore;
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||||
extern EVENT *gDmaEvent;
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||||
extern KDPC gDmaDpc;
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||||
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||||
void IdeDmaCompletionDpc(KDPC *dpc, void *context, void *systemArgument1, void *systemArgument2);
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||||
void IdeIsr(void);
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||||
void IdeWorker(uintptr_t arg);
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bool IdeDmaInit(void);
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||||
@@ -0,0 +1,87 @@
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||||
// ide_bus.c - Bus-master IDE PCI/DMA initialisation.
|
||||
#include "ide.h"
|
||||
|
||||
bool IdeDmaInit(void) {
|
||||
// ---- Find PCI IDE controller (class 0x01, subclass 0x01) --------------
|
||||
uint8_t bus, dev, fn;
|
||||
if (!gHal->Pci.FindClass(0x01, 0x01, &bus, &dev, &fn)) {
|
||||
DbgPrint("IDE DMA: No PCI IDE controller found — using PIO\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
// ---- Read BAR4 (Bus Master base, I/O space) ---------------------------
|
||||
// PCI config offset 0x20. Bit 0 must be 1 for I/O BAR.
|
||||
uint32_t bar4 = gHal->Pci.Read32(bus, dev, fn, 0x20);
|
||||
if (!(bar4 & 0x1)) {
|
||||
DbgPrint("IDE DMA: BAR4 is a memory BAR (0x%08x) — unexpected, using PIO\n", bar4);
|
||||
return false;
|
||||
}
|
||||
uint16_t bmBase = (uint16_t)(bar4 & 0xFFFC);
|
||||
if (bmBase == 0) {
|
||||
DbgPrint("IDE DMA: BAR4 is zero (firmware didn't assign it) — using PIO\n");
|
||||
return false;
|
||||
}
|
||||
DbgPrint("IDE DMA: Bus Master base = 0x%04X (bus %u, dev %u, fn %u)\n",
|
||||
bmBase, bus, dev, fn);
|
||||
|
||||
// ---- Enable Bus Mastering in PCI Command register (bit 2) ------------
|
||||
uint32_t pciCmd = gHal->Pci.Read32(bus, dev, fn, 0x04);
|
||||
gHal->Pci.Write32(bus, dev, fn, 0x04, pciCmd | (1u << 2));
|
||||
|
||||
// ---- Allocate PRDT page (must be 32-bit physical, 4-byte aligned) ----
|
||||
PHYSICAL_ADDRESS prdtPhys = MmAllocateContiguous(1);
|
||||
if (!prdtPhys) {
|
||||
DbgPrint("IDE DMA: Failed to allocate PRDT page\n");
|
||||
return false;
|
||||
}
|
||||
if (prdtPhys >> 32) {
|
||||
// MmAllocateContiguous returned memory above 4 GB — BM IDE can't
|
||||
// address it. This shouldn't happen on normal x86 systems with early
|
||||
// boot allocations but we check defensively.
|
||||
DbgPrint("IDE DMA: PRDT page is above 4 GB (0x%016llX) — using PIO\n",
|
||||
(uint64_t)prdtPhys);
|
||||
return false;
|
||||
}
|
||||
void *prdtVirt = gHal->PhysToVirt(prdtPhys);
|
||||
DbgPrint("IDE DMA: PRDT at phys 0x%08x, virt 0x%016llX\n", (uint32_t)prdtPhys, prdtVirt);
|
||||
|
||||
// ---- Create synchronisation objects ------------------------------------
|
||||
SEMAPHORE *sem = NULL;
|
||||
if (!KSUCCESS(KeSemaphoreCreate(0, 0x7FFFFFFF, &sem))) {
|
||||
DbgPrint("IDE DMA: Failed to create IRP semaphore\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
EVENT *dmaEv = NULL;
|
||||
if (!KSUCCESS(KeEventCreate(EventAutoReset, 0, &dmaEv))) {
|
||||
DbgPrint("IDE DMA: Failed to create DMA completion event\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
// ---- Commit module state -----------------------------------------------
|
||||
gBmBase = bmBase;
|
||||
gPrdtPhys = (uint32_t)prdtPhys;
|
||||
gPrdtVirt = (PRD *)prdtVirt;
|
||||
gIrpSemaphore = sem;
|
||||
gDmaEvent = dmaEv;
|
||||
KeInitializeDpc(&gDmaDpc, IdeDmaCompletionDpc, (void *)0);
|
||||
|
||||
IrpQueueInit(&gIrpQueue, sem);
|
||||
|
||||
// ---- Register IRQ 14 --------------------------------------------------
|
||||
KeIrqRegister(IDE_IRQ_PRIMARY, IdeIsr);
|
||||
DbgPrint("IDE DMA: IRQ %u registered\n", IDE_IRQ_PRIMARY);
|
||||
|
||||
// ---- Spawn worker thread -----------------------------------------------
|
||||
KSTATUS st = KeCreateKernelThread((uintptr_t)IdeWorker, 0,
|
||||
PriorityHigh, (THREAD **)NULL);
|
||||
if (!KSUCCESS(st)) {
|
||||
DbgPrint("IDE DMA: Worker thread creation failed (0x%x)\n", st);
|
||||
// Not fatal for init — the PRDT/IRQ are live but async callers will
|
||||
// never get completions. Better to surface the failure clearly.
|
||||
return false;
|
||||
}
|
||||
|
||||
DbgPrint("IDE DMA: Init complete\n");
|
||||
return true;
|
||||
}
|
||||
Reference in new issue
Block a user