KernelMain: more precise memory reporting, MmInitializePhysical: support more than ~1.1 GB of memory.
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@@ -1,159 +1,9 @@
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// ahci.c - AHCI SATA driver (basic PRDT, 1 slot, port 0)
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#include <io_driver.h>
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#include <hal_api.h>
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#include <mm_virt.h>
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#include <ke_status.h>
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#include <ke_debug.h>
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#include <stdint.h>
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#include <string.h>
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#include <intrin.h>
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// AHCI generic host control registers (BAR5 offsets).
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#define AHCI_GHC 0x04 // Global Host Control
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#define AHCI_PI 0x0C // Ports Implemented
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#define AHCI_PORT_BASE(p) (0x100 + (p) * 0x80)
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// Port registers (relative to port base).
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#define P_CLB 0x00 // Command List Base Address
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#define P_FB 0x08 // FIS Base Address
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#define P_IS 0x10 // Interrupt Status
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#define P_CMD 0x18 // Command and Status
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#define P_TFD 0x20 // Task File Data
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#define P_SIG 0x24 // Signature
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#define P_SSTS 0x28 // SATA Status
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#define P_CI 0x38 // Command Issue
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#define CMD_ST (1 << 0)
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#define CMD_FRE (1 << 4)
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#pragma pack(push, 1)
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typedef struct { uint8_t cfl:5,a:1,w:1,p:1; uint8_t pmport:4,r:1,b:1,c:1,rsvd:1; uint16_t prdtl;
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uint32_t prdbc; uint64_t ctba; uint32_t rsvd2[4]; } HBA_CMD_HEADER;
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typedef struct { uint64_t dba; uint32_t rsvd; uint32_t dbc:22, rsvd2:9, i:1; } HBA_PRDT;
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typedef struct { uint8_t cfis[64]; uint8_t acmd[16]; uint8_t rsvd[48]; HBA_PRDT prdt[1]; } HBA_CMD_TABLE;
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#pragma pack(pop)
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static const HAL_API* gHal;
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static volatile uint32_t* gAhci = (volatile uint32_t *)0;
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static HBA_CMD_HEADER* gCmdList = (HBA_CMD_HEADER *)0;
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static HBA_CMD_TABLE* gCmdTable = (HBA_CMD_TABLE *)0;
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static uint8_t* gFisBuf = (uint8_t *)0;
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static uint8_t gPort = 0;
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static uint64_t gSectors = 0;
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static inline uint32_t PRd(uint32_t off) {
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return *(volatile uint32_t *)((uint8_t *)gAhci + off);
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}
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static inline void PWr(uint32_t off, uint32_t v) {
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*(volatile uint32_t *)((uint8_t *)gAhci + off) = v;
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}
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static inline uint32_t PortRd(uint8_t p, uint32_t off) {
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return PRd(AHCI_PORT_BASE(p) + off);
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}
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static inline void PortWr(uint8_t p, uint32_t off, uint32_t v) {
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PWr(AHCI_PORT_BASE(p) + off, v);
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}
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static void AhciIssueCmd(uint8_t fis[20], void* buf, uint32_t bytes, int write) {
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// Fill FIS in command table.
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memcpy(gCmdTable->cfis, fis, 20);
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gCmdTable->prdt[0].dba = MmGetPhysicalAddress((uintptr_t)buf);
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gCmdTable->prdt[0].dbc = bytes - 1;
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gCmdTable->prdt[0].i = 1;
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gCmdList[0].cfl = 5; // FIS length in DWORDs
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gCmdList[0].w = write ? 1 : 0;
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gCmdList[0].prdtl = 1;
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gCmdList[0].prdbc = 0;
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gCmdList[0].ctba = MmGetPhysicalAddress((uintptr_t)gCmdTable);
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PortWr(gPort, P_CI, 1);
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while (PortRd(gPort, P_CI) & 1) _mm_pause();
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}
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static KSTATUS AhciRead(uint64_t lba, uint32_t count, void* buf) {
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uint8_t fis[20] = {0};
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fis[0] = 0x27; fis[1] = 0x80; // H2D, C=1
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fis[2] = 0x25; // READ DMA EXT
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fis[4] = (uint8_t)lba;
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fis[5] = (uint8_t)(lba >> 8);
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fis[6] = (uint8_t)(lba >> 16);
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fis[7] = 0x40; // LBA mode
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fis[8] = (uint8_t)(lba >> 24);
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fis[9] = (uint8_t)(lba >> 32);
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fis[10]= (uint8_t)(lba >> 40);
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fis[12]= (uint8_t)count;
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fis[13]= (uint8_t)(count >> 8);
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AhciIssueCmd(fis, buf, count * 512, 0);
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return STATUS_SUCCESS;
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}
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static KSTATUS AhciWrite(uint64_t lba, uint32_t count, const void* buf) {
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uint8_t fis[20] = {0};
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fis[0] = 0x27; fis[1] = 0x80;
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fis[2] = 0x35; // WRITE DMA EXT
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fis[4] = (uint8_t)lba;
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fis[5] = (uint8_t)(lba >> 8);
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fis[6] = (uint8_t)(lba >> 16);
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fis[7] = 0x40;
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fis[8] = (uint8_t)(lba >> 24);
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fis[9] = (uint8_t)(lba >> 32);
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fis[10]= (uint8_t)(lba >> 40);
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fis[12]= (uint8_t)count;
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fis[13]= (uint8_t)(count >> 8);
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AhciIssueCmd(fis, (void *)buf, count * 512, 1);
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return STATUS_SUCCESS;
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}
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KSTATUS DriverEntry(const HAL_API* hal) {
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DbgPrint("AHCI: Init\n");
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gHal = hal;
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uint8_t bus, dev, fn;
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if (!hal->Pci.FindClass(0x01, 0x06, &bus, &dev, &fn))
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return STATUS_NOT_FOUND; // no AHCI controller
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// BAR5 = AHCI base address.
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uint32_t bar5 = hal->Pci.ConfigRead32(bus, dev, fn, 0x24) & ~0xFU;
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if (!bar5) return STATUS_NOT_FOUND;
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gAhci = (volatile uint32_t *)(gHal->PhysToVirt(bar5));
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// Enable AHCI mode.
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PWr(AHCI_GHC, PRd(AHCI_GHC) | (1 << 31));
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// Find a port with a connected device.
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uint32_t pi = PRd(AHCI_PI);
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for (int p = 0; p < 32; p++) {
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if (!(pi & (1 << p))) continue;
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uint32_t ssts = PortRd((uint8_t)p, P_SSTS);
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if ((ssts & 0xF) != 3) continue; // DET: device present + PHY
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if (PortRd((uint8_t)p, P_SIG) != 0x00000101) continue; // SATA
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gPort = (uint8_t)p;
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goto found;
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}
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return STATUS_NOT_FOUND;
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found:
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// Allocate command list (1 header), FIS buffer, command table.
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gCmdList = (HBA_CMD_HEADER *)MmAllocatePool(4096);
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gFisBuf = (uint8_t *)MmAllocatePool(4096);
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gCmdTable = (HBA_CMD_TABLE *)MmAllocatePool(4096);
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if (!gCmdList || !gFisBuf || !gCmdTable) return STATUS_NO_MEMORY;
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memset(gCmdList, 0, 4096);
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memset(gFisBuf, 0, 4096);
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memset(gCmdTable,0, 4096);
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PortWr(gPort, P_CLB, (uint32_t)(MmGetPhysicalAddress((uintptr_t)gCmdList)));
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PortWr(gPort, P_FB, (uint32_t)(MmGetPhysicalAddress((uintptr_t)gFisBuf)));
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PortWr(gPort, P_CMD, PortRd(gPort, P_CMD) | CMD_FRE | CMD_ST);
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// Identify to get sector count.
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uint8_t fis[20] = {0};
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fis[0] = 0x27; fis[1] = 0x80; fis[2] = 0xEC;
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uint16_t ident[256];
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memset(ident, 0, sizeof(ident));
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AhciIssueCmd(fis, ident, 512, 0);
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gSectors = *(uint64_t *)(&ident[100]);
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if (!gSectors) gSectors = ((uint32_t)ident[61] << 16) | ident[60];
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DISK_DRIVER drv = { AhciRead, AhciWrite, gSectors };
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return IoRegisterDisk(1, &drv); // drive 1; drive 0 = IDE
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(void)hal;
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DbgPrint("AHCI: TODO.\n");
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return STATUS_SUCCESS;
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}
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@@ -6,4 +6,4 @@ KSTATUS DriverEntry(const HAL_API* hal) {
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(void)hal;
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DbgPrint("Test runtime driver\n");
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return STATUS_SUCCESS;
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}
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}
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