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maksw committed
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@@ -26,6 +26,7 @@ static uint32_t gPciDeviceCount;
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#define PCI_MMIO_VA_LIMIT 0xFFFF980000000000ULL
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static uintptr_t gPciMmioNext = PCI_MMIO_VA_BASE;
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static SPINLOCK gPciMmioLock = SPINLOCK_INIT;
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// Implements the align Up64 operation.
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static uint64_t PciAlignUp64(uint64_t value, uint64_t alignment) {
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@@ -43,13 +44,15 @@ static KSTATUS PciAllocateMmioVa(uint64_t length, uintptr_t* outVa) {
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return NTLSTATUS_INVALID_PARAMETER;
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uint64_t alignedLength = PciAlignUp64(length, NTL_DDK_PAGE_SIZE);
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uintptr_t cookie = KeAcquireSpinlock(&gPciMmioLock);
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uintptr_t va = (uintptr_t)PciAlignUp64((uint64_t)gPciMmioNext, NTL_DDK_PAGE_SIZE);
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if (va < PCI_MMIO_VA_BASE || va >= PCI_MMIO_VA_LIMIT)
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if (va < PCI_MMIO_VA_BASE || va >= PCI_MMIO_VA_LIMIT ||
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alignedLength > (uint64_t)(PCI_MMIO_VA_LIMIT - va)) {
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KeReleaseSpinlock(&gPciMmioLock, cookie);
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return NTLSTATUS_NO_MEMORY;
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if (alignedLength > (uint64_t)(PCI_MMIO_VA_LIMIT - va))
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return NTLSTATUS_NO_MEMORY;
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}
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gPciMmioNext = va + (uintptr_t)alignedLength;
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KeReleaseSpinlock(&gPciMmioLock, cookie);
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*outVa = va;
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return NTLSTATUS_SUCCESS;
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}
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@@ -601,77 +604,306 @@ static uint8_t PciFindCapability(PCI_PDO_EXTENSION* ext, uint8_t capId) {
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return offset;
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}
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// Enables msi.
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__declspec(dllexport) KSTATUS PciEnableMsi(DEVICE_OBJECT* pdo, uint8_t irqSlot) {
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// PCI owns message programming, while the kernel owns CPU/vector placement.
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typedef struct PCI_MESSAGE_CONTEXT {
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DEVICE_OBJECT* Pdo;
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uint32_t TableOffset;
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uint16_t Capability;
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uint8_t Msix;
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uint8_t Reserved;
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} PCI_MESSAGE_CONTEXT;
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static KSTATUS PciUpdateMessageRoute(void* opaque,
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KE_INTERRUPT_MESSAGE_OPERATION operation, const NTL_DDK_MSI_MESSAGE* message) {
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PCI_MESSAGE_CONTEXT* ctx = (PCI_MESSAGE_CONTEXT*)opaque;
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PCI_PDO_EXTENSION* ext;
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if (!PciIsPdo(pdo, &ext))
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return NTLSTATUS_INVALID_PARAMETER;
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if (irqSlot >= 24u)
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return NTLSTATUS_INVALID_PARAMETER;
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uint8_t cap = PciFindCapability(ext, PCI_CAP_ID_MSI);
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if (!cap)
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return NTLSTATUS_NOT_SUPPORTED;
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uint8_t bus = ext->Info.Address.Bus;
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uint8_t dev = ext->Info.Address.Device;
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if (!ctx || !PciIsPdo(ctx->Pdo, &ext)) return NTLSTATUS_INVALID_PARAMETER;
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uint8_t bus = ext->Info.Address.Bus, dev = ext->Info.Address.Device;
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uint8_t fn = ext->Info.Address.Function;
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uint16_t control = PciRawRead16(bus, dev, fn, (uint16_t)(cap + 2u));
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bool is64 = (control & PCI_MSI_CTRL_64BIT) != 0;
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bool pvm = (control & PCI_MSI_CTRL_PVM) != 0;
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NTL_DDK_MSI_MESSAGE message;
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KSTATUS messageStatus = KeIrqComposeMsiMessage(irqSlot, &message);
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if (!KSUCCESS(messageStatus))
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return messageStatus;
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PciRawWrite32(bus, dev, fn, (uint16_t)(cap + 4u), (uint32_t)message.Address);
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if (is64) {
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PciRawWrite32(bus, dev, fn, (uint16_t)(cap + 8u), (uint32_t)(message.Address >> 32));
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PciRawWrite16(bus, dev, fn, (uint16_t)(cap + 12u), (uint16_t)message.Data);
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if (pvm)
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PciRawWrite32(bus, dev, fn, (uint16_t)(cap + 16u), 0);
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} else {
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PciRawWrite16(bus, dev, fn, (uint16_t)(cap + 8u), (uint16_t)message.Data);
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if (pvm)
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PciRawWrite32(bus, dev, fn, (uint16_t)(cap + 12u), 0);
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if (ctx->Msix) {
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if (!ext->MsixTable || ctx->TableOffset > ext->MsixMappedLength ||
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ext->MsixMappedLength - ctx->TableOffset < 16u)
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return NTLSTATUS_DEVICE_ERROR;
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volatile uint32_t* entry = (volatile uint32_t*)(ext->MsixTable + ctx->TableOffset);
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if (operation == KeInterruptMessageQuiesce) {
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entry[3] = 1u;
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} else if (operation == KeInterruptMessageProgram && message) {
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entry[0] = (uint32_t)message->Address;
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entry[1] = (uint32_t)(message->Address >> 32);
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entry[2] = message->Data;
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} else if (operation == KeInterruptMessageResume) {
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entry[3] = 0u;
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} else return NTLSTATUS_INVALID_PARAMETER;
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(void)entry[3];
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return NTLSTATUS_SUCCESS;
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}
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control &= (uint16_t)~PCI_MSI_CTRL_MME_MASK;
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control |= PCI_MSI_CTRL_ENABLE;
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PciRawWrite16(bus, dev, fn, (uint16_t)(cap + 2u), control);
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uint16_t cmd = PciRawRead16(bus, dev, fn, PCI_REG_COMMAND_STATUS);
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cmd |= PCI_COMMAND_INTX_DISABLE;
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PciRawWrite16(bus, dev, fn, PCI_REG_COMMAND_STATUS, cmd);
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DbgPrint("pci: MSI enabled %02x:%02x.%u cap=0x%02x vector=0x%02x irqslot=%u %s\n",
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bus, dev, fn, cap, (unsigned)(message.Data & 0xFFu), irqSlot, is64 ? "64-bit" : "32-bit");
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uint16_t control = PciRawRead16(bus, dev, fn, ctx->Capability + 2u);
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bool is64 = (control & PCI_MSI_CTRL_64BIT) != 0;
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// MSI per-vector masking preserves pending messages during retargeting.
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// Devices without PVM retain their initial affinity until disconnect.
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if (!(control & PCI_MSI_CTRL_PVM)) return NTLSTATUS_NOT_SUPPORTED;
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uint16_t maskOffset = ctx->Capability + (is64 ? 16u : 12u);
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if (operation == KeInterruptMessageQuiesce) {
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uint32_t mask = PciRawRead32(bus, dev, fn, maskOffset);
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PciRawWrite32(bus, dev, fn, maskOffset, mask | 1u);
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(void)PciRawRead32(bus, dev, fn, maskOffset);
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} else if (operation == KeInterruptMessageProgram && message) {
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PciRawWrite32(bus, dev, fn, ctx->Capability + 4u, (uint32_t)message->Address);
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if (is64) {
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PciRawWrite32(bus, dev, fn, ctx->Capability + 8u,
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(uint32_t)(message->Address >> 32));
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PciRawWrite16(bus, dev, fn, ctx->Capability + 12u, (uint16_t)message->Data);
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} else PciRawWrite16(bus, dev, fn, ctx->Capability + 8u, (uint16_t)message->Data);
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} else if (operation == KeInterruptMessageResume) {
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uint32_t mask = PciRawRead32(bus, dev, fn, maskOffset);
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PciRawWrite32(bus, dev, fn, maskOffset, mask & ~1u);
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(void)PciRawRead32(bus, dev, fn, maskOffset);
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} else return NTLSTATUS_INVALID_PARAMETER;
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(void)PciRawRead16(bus, dev, fn, ctx->Capability + 2u);
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return NTLSTATUS_SUCCESS;
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}
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// Enables a single MSI vector, allocating the nt-lite IRQ slot internally.
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__declspec(dllexport) KSTATUS PciEnableMsiAuto(DEVICE_OBJECT* pdo, uint8_t* outIrqSlot) {
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PCI_PDO_EXTENSION* ext;
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if (!outIrqSlot || !PciIsPdo(pdo, &ext))
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return NTLSTATUS_INVALID_PARAMETER;
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if (!PciFindCapability(ext, PCI_CAP_ID_MSI))
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return NTLSTATUS_NOT_SUPPORTED;
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uint8_t irq = 0xFFu;
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KSTATUS st = KeIrqAllocateMsiVector(&irq);
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if (!KSUCCESS(st))
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static KSTATUS PciBindMessage(DEVICE_OBJECT* pdo, PCI_INTERRUPT_REQUEST* request,
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uint8_t msix, uint16_t capability, uint32_t tableOffset) {
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PCI_MESSAGE_CONTEXT* ctx = (PCI_MESSAGE_CONTEXT*)MmAllocatePool(sizeof(*ctx));
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if (!ctx) return NTLSTATUS_NO_MEMORY;
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ctx->Pdo = pdo;
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ctx->Msix = msix;
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ctx->Capability = capability;
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ctx->TableOffset = tableOffset;
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ctx->Reserved = 0;
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KSTATUS st = KeInterruptBindMessageSource(request->Interrupt, PciUpdateMessageRoute, ctx);
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if (!KSUCCESS(st)) {
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MmFreePool(ctx);
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return st;
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st = PciEnableMsi(pdo, irq);
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if (!KSUCCESS(st))
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return st;
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*outIrqSlot = irq;
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}
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request->BusContext = ctx;
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return NTLSTATUS_SUCCESS;
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}
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// Programs a pre-allocated interrupt group. All routes exist before device delivery begins.
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static KSTATUS PciConnectMsix(DEVICE_OBJECT* pdo, PCI_PDO_EXTENSION* ext,
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PCI_INTERRUPT_REQUEST* requests, uint32_t count) {
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uint8_t cap = PciFindCapability(ext, PCI_CAP_ID_MSIX);
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if (!cap) return NTLSTATUS_NOT_SUPPORTED;
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uint8_t bus = ext->Info.Address.Bus, dev = ext->Info.Address.Device;
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uint8_t fn = ext->Info.Address.Function;
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uint16_t control = PciRawRead16(bus, dev, fn, cap + 2u);
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uint32_t size = (control & 0x7FFu) + 1u;
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if (count > size) return NTLSTATUS_NOT_SUPPORTED;
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uint32_t table = PciRawRead32(bus, dev, fn, cap + 4u);
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uint32_t bir = table & 7u, offset = table & ~7u;
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if (bir >= PCI_MAX_BARS) return NTLSTATUS_DEVICE_ERROR;
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PCI_BAR bar;
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KSTATUS st = PciGetBar(pdo, (uint8_t)bir, &bar);
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if (!KSUCCESS(st) || (bar.Type != PciBarMemory32 && bar.Type != PciBarMemory64) ||
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bar.Length < offset || count > (bar.Length - offset) / 16u)
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return NTLSTATUS_NOT_SUPPORTED;
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uint16_t command = PciRawRead16(bus, dev, fn, PCI_REG_COMMAND_STATUS);
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if (!(command & PCI_COMMAND_MEMORY_SPACE)) {
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DbgPrint("pci: MSI-X requires enabled memory decoding at %02x:%02x.%u\n",
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bus, dev, fn);
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return NTLSTATUS_DEVICE_ERROR;
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}
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if (!ext->MsixTable) {
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volatile uint8_t* mapped = (volatile uint8_t*)0;
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uint64_t mappedLength = 0;
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st = PciMapBar(pdo, (uint8_t)bir,
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NTL_DDK_PAGE_PRESENT | NTL_DDK_PAGE_WRITE | NTL_DDK_PAGE_CACHE_UC | NTL_DDK_PAGE_NX,
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(void**)&mapped, &mappedLength);
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if (!KSUCCESS(st)) return st;
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ext->MsixTable = mapped;
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ext->MsixMappedLength = mappedLength;
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ext->MsixBarIndex = (uint8_t)bir;
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}
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// A persistent per-PDO mapping prevents repeated BAR allocations on reconnect.
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if (ext->MsixBarIndex != bir || ext->MsixMappedLength < offset ||
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count > (ext->MsixMappedLength - offset) / 16u)
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return NTLSTATUS_DEVICE_ERROR;
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volatile uint8_t* mapped = ext->MsixTable;
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// Mask the function and turn off stale firmware MSI before programming MSI-X.
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PciRawWrite16(bus, dev, fn, cap + 2u, (control | 0x4000u) & ~0x8000u);
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uint8_t msiCap = PciFindCapability(ext, PCI_CAP_ID_MSI);
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if (msiCap) {
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uint16_t msiControl = PciRawRead16(bus, dev, fn, msiCap + 2u);
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PciRawWrite16(bus, dev, fn, msiCap + 2u,
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msiControl & (uint16_t)~PCI_MSI_CTRL_ENABLE);
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}
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for (uint32_t i = 0; i < count; i++) {
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st = KeInterruptReserveMessage(requests[i].Affinity, requests[i].Routine,
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requests[i].Context, &requests[i].Interrupt);
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if (!KSUCCESS(st)) goto failed;
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NTL_DDK_MSI_MESSAGE msg;
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st = KeInterruptComposeMessage(requests[i].Interrupt, &msg);
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if (!KSUCCESS(st)) goto failed;
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st = PciBindMessage(pdo, &requests[i], 1u, cap, offset + 16u * i);
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if (!KSUCCESS(st)) goto failed;
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volatile uint32_t* entry = (volatile uint32_t*)(mapped + offset + 16u * i);
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entry[3] = 1u;
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entry[0] = (uint32_t)msg.Address;
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entry[1] = (uint32_t)(msg.Address >> 32);
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entry[2] = msg.Data;
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entry[3] = 0u;
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// Read back the entry to drain posted MMIO writes before enabling MSI-X.
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(void)entry[3];
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}
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PciRawWrite16(bus, dev, fn, cap + 2u, (control | 0x8000u) & ~0x4000u);
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(void)PciRawRead16(bus, dev, fn, cap + 2u);
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PciRawWrite16(bus, dev, fn, PCI_REG_COMMAND_STATUS, command | PCI_COMMAND_INTX_DISABLE);
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for (uint32_t i = 0; i < count; i++) {
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st = KeInterruptActivateMessage(requests[i].Interrupt);
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if (!KSUCCESS(st)) goto failed;
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}
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return NTLSTATUS_SUCCESS;
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failed:
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PciRawWrite16(bus, dev, fn, cap + 2u, control & ~0x8000u);
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for (uint32_t i = 0; i < count; i++) {
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if (requests[i].Interrupt) {
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KeInterruptDisconnect(requests[i].Interrupt);
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requests[i].Interrupt = (KE_INTERRUPT*)0;
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}
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if (requests[i].BusContext) {
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MmFreePool(requests[i].BusContext);
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requests[i].BusContext = 0;
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}
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}
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return st;
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}
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static KSTATUS PciConnectMsi(DEVICE_OBJECT* pdo, PCI_PDO_EXTENSION* ext,
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PCI_INTERRUPT_REQUEST* request) {
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uint8_t cap = PciFindCapability(ext, PCI_CAP_ID_MSI);
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if (!cap) return NTLSTATUS_NOT_SUPPORTED;
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uint8_t bus = ext->Info.Address.Bus, dev = ext->Info.Address.Device;
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uint8_t fn = ext->Info.Address.Function;
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KSTATUS st = KeInterruptReserveMessage(request->Affinity, request->Routine,
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request->Context, &request->Interrupt);
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if (!KSUCCESS(st)) return st;
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NTL_DDK_MSI_MESSAGE msg;
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st = KeInterruptComposeMessage(request->Interrupt, &msg);
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if (!KSUCCESS(st)) goto failed;
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st = PciBindMessage(pdo, request, 0u, cap, 0);
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if (!KSUCCESS(st)) goto failed;
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uint8_t msixCap = PciFindCapability(ext, PCI_CAP_ID_MSIX);
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if (msixCap) {
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uint16_t msixControl = PciRawRead16(bus, dev, fn, msixCap + 2u);
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PciRawWrite16(bus, dev, fn, msixCap + 2u,
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(msixControl | 0x4000u) & (uint16_t)~0x8000u);
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}
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uint16_t control = PciRawRead16(bus, dev, fn, cap + 2u);
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bool is64 = (control & PCI_MSI_CTRL_64BIT) != 0;
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bool pvm = (control & PCI_MSI_CTRL_PVM) != 0;
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PciRawWrite32(bus, dev, fn, cap + 4u, (uint32_t)msg.Address);
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if (is64) {
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PciRawWrite32(bus, dev, fn, cap + 8u, (uint32_t)(msg.Address >> 32));
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PciRawWrite16(bus, dev, fn, cap + 12u, (uint16_t)msg.Data);
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if (pvm) PciRawWrite32(bus, dev, fn, cap + 16u, 0);
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} else {
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PciRawWrite16(bus, dev, fn, cap + 8u, (uint16_t)msg.Data);
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if (pvm) PciRawWrite32(bus, dev, fn, cap + 12u, 0);
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}
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control = (control & ~(uint16_t)PCI_MSI_CTRL_MME_MASK) | PCI_MSI_CTRL_ENABLE;
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PciRawWrite16(bus, dev, fn, cap + 2u, control);
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uint16_t command = PciRawRead16(bus, dev, fn, PCI_REG_COMMAND_STATUS);
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PciRawWrite16(bus, dev, fn, PCI_REG_COMMAND_STATUS, command | PCI_COMMAND_INTX_DISABLE);
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st = KeInterruptActivateMessage(request->Interrupt);
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if (!KSUCCESS(st)) goto failed;
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return NTLSTATUS_SUCCESS;
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failed:
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{
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uint16_t previous = PciRawRead16(bus, dev, fn, cap + 2u);
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PciRawWrite16(bus, dev, fn, cap + 2u,
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previous & (uint16_t)~PCI_MSI_CTRL_ENABLE);
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}
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KeInterruptDisconnect(request->Interrupt);
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request->Interrupt = (KE_INTERRUPT*)0;
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if (request->BusContext) {
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MmFreePool(request->BusContext);
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request->BusContext = 0;
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}
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return st;
|
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}
|
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__declspec(dllexport) KSTATUS PciConnectInterrupts(DEVICE_OBJECT* pdo,
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PCI_INTERRUPT_REQUEST* requests, uint32_t count, bool* usingMessages) {
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PCI_PDO_EXTENSION* ext;
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if (!PciIsPdo(pdo, &ext) || !requests || !count || !usingMessages)
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return NTLSTATUS_INVALID_PARAMETER;
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*usingMessages = false;
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for (uint32_t i = 0; i < count; i++) {
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if (!requests[i].Routine) return NTLSTATUS_INVALID_PARAMETER;
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requests[i].Interrupt = (KE_INTERRUPT*)0;
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requests[i].BusContext = 0;
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}
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KSTATUS st = PciConnectMsix(pdo, ext, requests, count);
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if (KSUCCESS(st)) { *usingMessages = true; return st; }
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if (count > 1u) return st;
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st = PciConnectMsi(pdo, ext, requests);
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if (KSUCCESS(st)) { *usingMessages = true; return st; }
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uint8_t line = ext->Info.InterruptLine;
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uint8_t pin = ext->Info.InterruptPin;
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if (pin < 1u || pin > 4u || line == 0u || line == 0xFFu) {
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DbgPrint("pci: INTx resource unavailable for %02x:%02x.%u pin=%u line=%u\n",
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ext->Info.Address.Bus, ext->Info.Address.Device,
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ext->Info.Address.Function, pin, line);
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return NTLSTATUS_NOT_FOUND;
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}
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// The Interrupt Line register is a firmware hint until PCI _PRT routing is available.
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DbgPrint("pci: INTx legacy route %02x:%02x.%u pin=%u line=%u\n",
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ext->Info.Address.Bus, ext->Info.Address.Device,
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ext->Info.Address.Function, pin, line);
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if (line < 16u)
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st = KeInterruptConnectIsa(line, 0x0Fu, requests[0].Affinity,
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requests[0].Routine, requests[0].Context, &requests[0].Interrupt);
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else
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st = KeInterruptConnectGsi(line, 0x0Fu, requests[0].Affinity,
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requests[0].Routine, requests[0].Context, &requests[0].Interrupt);
|
||||
if (KSUCCESS(st)) {
|
||||
uint16_t command = PciRawRead16(ext->Info.Address.Bus,
|
||||
ext->Info.Address.Device, ext->Info.Address.Function, PCI_REG_COMMAND_STATUS);
|
||||
PciRawWrite16(ext->Info.Address.Bus, ext->Info.Address.Device,
|
||||
ext->Info.Address.Function, PCI_REG_COMMAND_STATUS,
|
||||
command & (uint16_t)~PCI_COMMAND_INTX_DISABLE);
|
||||
}
|
||||
return st;
|
||||
}
|
||||
|
||||
__declspec(dllexport) void PciDisconnectInterrupts(DEVICE_OBJECT* pdo,
|
||||
PCI_INTERRUPT_REQUEST* requests, uint32_t count) {
|
||||
PCI_PDO_EXTENSION* ext;
|
||||
if (!PciIsPdo(pdo, &ext) || !requests) return;
|
||||
// Close every route before disabling PCI delivery so an affinity update
|
||||
// cannot resume the device after its disconnect has begun.
|
||||
for (uint32_t i = 0; i < count; i++)
|
||||
if (requests[i].Interrupt) KeInterruptBeginDisconnect(requests[i].Interrupt);
|
||||
uint8_t bus = ext->Info.Address.Bus, dev = ext->Info.Address.Device;
|
||||
uint8_t fn = ext->Info.Address.Function;
|
||||
uint8_t msi = PciFindCapability(ext, PCI_CAP_ID_MSI);
|
||||
uint8_t msix = PciFindCapability(ext, PCI_CAP_ID_MSIX);
|
||||
if (msi) {
|
||||
uint16_t control = PciRawRead16(bus, dev, fn, msi + 2u);
|
||||
PciRawWrite16(bus, dev, fn, msi + 2u, control & ~PCI_MSI_CTRL_ENABLE);
|
||||
}
|
||||
if (msix) {
|
||||
uint16_t control = PciRawRead16(bus, dev, fn, msix + 2u);
|
||||
PciRawWrite16(bus, dev, fn, msix + 2u, (control | 0x4000u) & ~0x8000u);
|
||||
}
|
||||
uint16_t command = PciRawRead16(bus, dev, fn, PCI_REG_COMMAND_STATUS);
|
||||
PciRawWrite16(bus, dev, fn, PCI_REG_COMMAND_STATUS, command | PCI_COMMAND_INTX_DISABLE);
|
||||
for (uint32_t i = 0; i < count; i++) {
|
||||
if (requests[i].Interrupt) {
|
||||
KeInterruptDisconnect(requests[i].Interrupt);
|
||||
requests[i].Interrupt = (KE_INTERRUPT*)0;
|
||||
}
|
||||
if (requests[i].BusContext) {
|
||||
MmFreePool(requests[i].BusContext);
|
||||
requests[i].BusContext = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static KSTATUS DriverInitialize(NTL_MODULE* module) {
|
||||
(void)module;
|
||||
|
||||
|
||||
Reference in new issue
Block a user